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datasheet r8a66593 fp/bg assp (usb2.0 peripheral controller) r19ds0071ej0101 rev1.01 p age 1 of 142 jun 28,2013 r19ds0071ej0101 rev1.01 jun 28,2013 1 overview 1.1 overview the r8a66593 is a universal serial bus (usb) peripheral controller that is compliant with usb specification rev ision 2.0 for hi - speed and full - speed transfer. this controller has a built - in usb transceiver and i s compatible with all the transfer types defined in usb specification rev ision 2.0. the internal buffer memory is 8.5k , and a maximum ten pipes can be used for transferring data. for p ipe1 to pipe 9, any endpoint address can be assigned matching u ser s yste m. separate bus or multiplex bus can be selected for the cpu connection. a s plit bus interface (exclusively for the dma interface) that is different from the cpu bus interface is provided and is suitable for system s demanding high - performance data transfer . 1.2 features 1.2.1 usb rev2.0 hi - speed supported ? complient with usb specification rev. 2.0 ? both hi - speed transfer(480mbs)and full - speed transfer(12mbps) are supported ? built - in hi - speed / full - speed usb transceiver ? can be operated as a hi - speed / full - speed usb per ipheral controller 1.2.2 low power consumption ? 1.5v core power consumes l ess power when operati ng ? with the installed low power sleep mode functions, less power is consumed when the usb is not in use, which is also applicable for portable device s ? standby power c onsumption can be greatly reduced by keeping only the vif power source on when not using the usb function. ? operation al with a 3.3v single power supply using the internal 1.5v core power regulator 1.2.3 space - saving package ? few external device s and space - saving package ? vbus signal can be connected directly to the controller input pin ? built - in d+ p ull -u p resist or ? built - in d+ and d - terminating resist ors ( for hi - speed operations) ? built - in d+ and d - output resist ors ( for full - speed operations)
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 2 of 142 jun 28,2013 1.2.4 compatible w ith a ll usb t ransfer types ? compatible with all usb transfer types , including isochronous transfer ? control transfer ? bulk transfer ? interrupt transfer ( n ot compatible with h igh -b andwidth) ? isochronous transfer ( n ot compatible with h igh -b andwidth) 1.2.5 bus i nterface ? the user can select either a 1.8v or 3.3v bus interface power ? 16- bit cpu bus interface ? compatible with 16 - bit separate bus/16 - bit multiplex bus ? compatible with dma transfer in 8 - bit/16 - bit access (s lave function) ? 8 - bit split bus ( e xclusive f or external direct memory access controller (dmac) ) interface ? built - in two dma interface channels ? dma transfer provides 40m b /second high - performance data transfer 1.2.6 pipe c onfiguration ? built - in 8.5k b buffer memory for usb communication ? maximum of ten pipes c an be selected ( i ncluding default control pipe) ? programmable pipe configuration ? any endpoint address can be assigned to p ipe1 to pipe 9 ? transfer conditions that can be written for each pipe ? pipe0: control transfer, single buffer fixed at 256 byte s ? pipe 1~pipe2: bulk transfer/ i sochronous transfer , continuous transfer mode s . programmable buffer size ( specifiable up to 2k bytes per side, double buffer also specifiable ) ? pipe3~pipe5: bulk transfer, continuous transfer mode s , programmable buffer size ( specifiable up to 2k bytes per side, double buffer also specifiable ) ? pipe6~pipe9: interrupt transfer, single buffer fixed at 64 bytes 1.2.7 other functions ? auto identification of hi - speed or full - speed operations according to res et handshake auto response ? compatible with the cpu of b ig -e ndian or l ittle - e ndian according to the b yte -e ndian s wap function ? this function can be set against each fifo port ? transfer end function according to transaction count ? this function can be set a gainst each pipe. ? end function of dma transfer by external trigger (dend pin) ? control transfer stage management function ? device state management function ? auto response function related to set_address request ? nak response interrupt function (nrdy) ? sof inter polation function ? sof plus output function ? three types of i nput clock can be selected by built - in pll ? select from 48mhz/24mhz/12mhz ? function to modify the brdy interrupt event notification timing (bfre) ? function to clear the auto buffer memory after the pipe data specified in the dxfifo port is read (dclrm) ? function to provide the a uto c lock from c lock s top status ? nak setting function (shtnak) for pid response corresponding to t ransfer e nd 1.2.8 applications digital video cameras, digital still cameras, printers, external storage devices, portable information terminals, usb audio devices also: generalordinary pc peripheral devices equipped with hi - speed usb
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 3 of 142 jun 28,2013 1.3 package 1.3.1 p in layout figure 1.1 and figure 1.2 shows the pin layout (top view) for this controller. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 dp0 62 39 dm0 63 38 gnd 64 37 nc 65 36 nc 66 35 vcc 67 34 gnd 68 33 gnd 69 32 gnd 70 31 nc 71 30 nc 72 29 gnd 73 28 nc 74 27 refrin 75 26 agnd 76 25 avcc 77 24 xout 78 23 xin 79 22 vcc 80 21 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 R8A66593FP dack0_n dend0_n dreq1_n dack1_n top view vif int_n sof_n dreq0_n vcc gnd vbus gnd a3 a2 a1 mpbus a4 vdd d5/ad5 d6/ad6 d13 d14 d7/ad7 vif gnd d8 d15 gnd d9 d10 d11 d12 d0 d1/ad1 d2/ad2 sd5 dend1_n vdd gnd sd0 d3/ad3 d4/ad4 sd6 sd7 vif sd1 sd2 sd3 sd4 gnd gnd rst_n rd_n a7/ale a6 a5 vif cs_n wr1_n wr0_n figure 1 . 1 r8a6659 3 fp pin l ayout ? the ?_n? in the signal name indicates that the signal is in the ?l? active state. package R8A66593FP : plqp0080la - a : 80pinlqfp (0.4mm pitch)
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 4 of 142 jun 28,2013 1 2 3 4 5 6 7 8 9 a gnd d15 d14 d10 gnd d5/ad5 d2/ad2 d0 gnd a b vif int_n d13 d11 vif d4/ad4 d1/ad1 cs_n vif b c dreq0_n dack0_n sof_n d9 d7/ad7 d3/ad3 wr1_n wr0_n rd_n c d dreq1_n dack1_n dend0_n d12 d8 d6/ad6 a6 a4 a5 d e gnd vdd dend1_n sd0 gnd a7/ale a3 vdd gnd e f sd2 sd3 sd4 sd1 nc a2 gnd mpbus a1 f g sd5 sd6 avcc nc gnd nc gnd rst_n vcc g h vif sd7 xin agnd vcc gnd gnd gnd vbus h j gnd vcc xout refrin nc nc gnd dm0 dp0 j 1 2 3 4 5 6 7 8 9 r8a66593bg ( top view ) figure 1 . 2 r8a6659 3 bg pin l ayout ? the ?_n? in the signal name indicates th at the signal is in the ?l? active package r8a66593bg : plbg0081ka - a : 81pinlfbga (0.5mm pitch)
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 5 of 142 jun 28,2013 1.4 pin description pin des cription s are given in table 1.1 , and the processing method of unused pins is given in table 1.2 . table 1 . 1 pin description cl assification pin n ame name i/o function number of pins pin status *5) being r eset immediately after reset cpu bus interface d15 - 0 data bus i/o this is a 16 - bit data bus. 16 *2) *2) ad7 -1 multiplex address bus i/o when selecting to the multiplex bus, these pins are used in the time division as a part of the data bus (d7 - d1) or address bus (a7 - a1). a7 - 1 address bus in this is the address bus. a0 does not exi st for the 16 - bit data bus. 7 input *3) input *3) ale address latch enabled in while selecting to the multiplex bus, the a7 pin is used as an ale signal. input inp ut cs_n chip select in the controller is selected in "l" level. 1 input *4) input *4) rd_n read strobe in reads the data from the register of this controller i n " l" level. 1 input input wr0_n d7 - 0 byte write strobe in writes d7 - d0 in the register of this controller at the rising edge. 1 input *4) input *4) wr1_n d15 - 8 b y te write strobe in writes d15 - d8 in the register of this controller at the rising edge. 1 input *4) input *4) mpbus bus mode selection in this is a separate bus in "l" level. this is a multiplex bus in "h" level. fix either "h" or "l" level. 1 input *1) input *1) split bus interface sd7 - 0 split data bus i/o when the split bus is selected, it functions as the split data bus. 8 input (hi - z) input (hi - z) dma bus interface dreq0_n dreq1_n dma request out notifies the dma transfer request of d0fifo port and d1fifo port. 2 h h dack0_n dack1_n dma acknowledgeme nt in enter the dma acknowledgement signal of d0fifo port and d1fifo port. 2 input input dend0_n dend1_n dma transfer end i/o for fifo port access write direction: receives transmission completion signal as an input signal from other chips or cpu. for fifo port access r ead direction: shows the last transmitted data as an output signal. 2 input (hi - z) input (hi - z) interrupt/ sof output int_n interrupt out notifies various types of interrupts related to usb communication by "l" active. active is by default "l" active, h owever it can be changed to "h" active by modifying the s etup value of inta bit in the software. 1 h h sof_n sof plus e output out when an sof is detect ed , outputs an sof pulse by "l" active. 1 h h clock xin input for oscillation in connect crystal osc illator between xin and xout. connect external clock signal to xin in order to input external clock, and leave open xout. 1 xout output for oscillation out 1 system control rst_n reset signal in reset s this controller at "l" level. 1 input (l) inpu t (h) usb bus interface dp0 usb d+ data i/o connect to d+ pin of usb bus. 1 input (hi - z) input (hi - z) dm0 usb d - data i/o connect to d - pin of usb bus. 1 input (hi - z) input (hi - z)
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 6 of 142 jun 28,2013 cl assification pin n ame name i/o function number of pins pin status *5) being r eset immediately after reset vbus m onitoring input vbus vbus input in connect directly to vbus of usb bus. can detect vbus connection/disconnection. connect to 5v when not connecting to vbus. 1 input (hi - z) input (hi - z) reference resistance refrin reference input in connect to analog gnd pin through 5.6k?1% resist or . 1 power /gnd avcc analog power - connect to 3.3v . 1 agnd analog gnd - 1 vcc power - connect to 3.3v . 3 gnd gnd - 13 (fp) 1 4 ( bg) vif io power - connect to 3.3v or 1.8v. 4 vdd core power out output 1.5v with internal regulator ? generated. for stability core power, connect the 4.7uf and 0.1uf capacitor between gnd. no connection of external power is necessary. 2 *1) the input level of mpbus pin must be fixed. do not switch the level during controller operations. *2) pin is for output when cs n = ?l ? and rd n= ?l ? , otherwise input. *3) hi - z input (open) is enabled when mpbus = ?h ?. *4) maintain status (a) or (b) as described below during reset and immediately after reset release for cs _ n, wr0 _ n an d wr1 _ n signals. (a) cs_n = ?h ? (b) wr0 n = ?h ? and wr1_n = ? h ? *5) explanations for ? pin status ? column (a) input: input port, hi - z status (open) disabled (b) input (hi - z): input port, hi - z status (open) enabled (c) h, l, h/l: indicates output port status table 1 . 2 example of u nused r8a6659 3 pin classification pin n ame process c ontents split bus interface sd7 - 0 open dma bus interface dreq0_n, dreq1_n open dack0_n, dack1_n fixed to vif ? h ? level *1) dend0_n, dend1_n open *2) sof ouptput sof_n open vbus monitor input vbus connect to vbus signal on usb connector *1) when not using dackn_n pin, set dma x cfg register dfo r m bit to ?000? and dacka bit to ?0? (n=0, 1) *2) when not using dendn_n pin, set dma x cfg register dende bit to ?0? (n=0, 1)
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 7 of 142 jun 28,2013 1.5 structure of pin functions block diagram of the controller pin functions is shown in figure 1.3 . cpu bus interface d15 - 8, d7 - 1(/ad7 - 1), d0 a7/ale, a6 - 1 cs_n rd_n wr0_n wr1_n mpbu s interrupt /sof output int_n sof_n dma interface dreq0_n dack0_n dend0_n dreq1_n dack1_n dend1_n split bus sd7 - 0 system control rst_n 16 7 clock xin xout vbus monitoring input vbus usb interface 0 dp0, dm0 reference resistance refrin r8a66593 8 2 figure 1 . 3 block d iagram of pin f unctions
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 8 of 142 jun 28,2013 1.6 functional o verview 1.6.1 bus i nterface the controller is compatible with the bus interfaces given below. 1.6.1.1 external b us i nterface the cpu accesses the control register of the controller us ing the cpu bus interface. there are two types of access below for the b us interface from the cpu. access using a chip select pin (cs_n) and three strobe pins (rd_n, wr0_n and wr1_n). (1) 16- bit separate bus seven address buses (a7 - 1) and sixteen data buse s (d15 - 0) are used. (2) 16- bit multiplex bus the ale pin (ale) and sixteen data buses (d15 - 0) are used. the d ata bus uses the address and data in the time division. separate bus or multiplex bus are selected at the mpbus pin signal level while canceling th e hardware reset. 1.6.1.2 fifo b uffer m emory a ccess m ethod this controller is compatible with the following two access types as an access method of the fifo buffer memory for usb data transmission. read ( w rite) of the data from the fifo buffer memory is possible by accessing ( r ead/ w rite) the fifo port from the cpu (dmac). (1) cpu access write the data in, or read the data from, the fifo buffer memory using the address signal and control signal. (2) dma access write the data in the fifo buffer memory from the cpu? s built -i n dmac or dedicated dmac, or read the data from the fifo buffer memory. usb communication is executed by a l ittle e ndian. a b yte e ndian swap function is provided in the fifo port access. for 16- bit access, the e ndian can be changed according to what is wr itten to the register. 1.6.1.3 fifo buffer memory access method from dmac to access the fifo buffer memory through the dma access, select an access method from the following : (1) method of using common bus with cpu (2) method in which dedicated bus (split bus) is used 1.6.2 u sb e vent the controller notifies the events regarding usb operations to the u ser s ystem through the interrupt. it also notifies that the dma interface can access the buffer memory of the selected pipe by asserting the dreq signal. depending on what the sof tware writes, i nterrupt notification activation can be selected for the type and factor.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 9 of 142 jun 28,2013 1.6.3 usb d ata t ransfer all types of data transfer of usb communication, such as control transfer, bulk transfer, interrupt transfer and isochronous transfer , are possible with this controller. the following are the pipe resources for each transfer type : (1) control transfer dedicated pipe - 1 (2) interrupt transfer dedicated pipe s - 4 (3) bulk transfer dedicated pipe s - 3 (4) bulk transfer or isochronous transfer selection pipe s - 2 write the usb transfer requirements for each pipe , such as transfer type, endpoint address , max imum packet size, etc. , according to the u ser s ystem. this controller is equipped with an 8.5kb buffer memory. a llocate the buffer memory according to the u ser s ystem or execute the settings such as buffer operation mode , for the bulk transfer dedicated pipe, and bulk transfer or isochronous transfer selection pipe. in buffer operations mode, high - performance data transfer with low interrupt frequency is possible by us ing a double buffer configuration or continuous transfer function of the data packet . a transfer completion function has been added, using the transaction counter function for efficient data transfer rates of bulk and isochronous transfer pipes. the u ser s ystem control cpu and dma controller access the buffer memory through three fifo port registers. 1.6.4 interface for access from dmac the dma interface is the data transfer between the u ser s ystem and this controller, in which the dxfifo port is used, and it i s a data transfer that does not us e the cpu. this controller is equipped with 2 - ch dma interface and includes the following functions : (1) transfer end notification function corresponding to the transfer end signal (dend signal) (2) fifo buffer auto clear function while receiving a zero - length packet this controller is equipped with an interface compatible with the two types of dma transfers given below : (1) cycle s teal t ransfer assert and n egate of the dreq pin is repeatedly transmitted for one data transmission (1 b yte/1 word). (2) burst t ransmission this is a transmission in which the dreq pin is asserted (not negated) until the transmission is completed, due to the pipe buffer memory area allocated to the fifo port or dend signal. "cs_n, rd_n and wr_n" or dack_n can b e selected as the handshake signal ( pin ) of the dma interface. high - performance dma transmission is possible in the dma transmission by a split bus by modifying the data s etup timing using an obus bit operation of the dmaxcfg register. 1.6.5 sof pulse o utput f u nction this controller is equipped with an sof pulse output function that notif ies the sof packet s end/ r eceive timing. a pulse is output from the sof_n pin at receiving the sof packet. when the sof packet is damaged, a pulse is output within the specified period according to the sof interpolation timer.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 10 of 142 jun 28,2013 1.6.6 importing the e xternal devices this controller is equipped with the external devices listed below . also, as the vbus pin has 5v - tolerant, the u ser s ystem can connect the vbus signal directly to this contro ller. (1) resistors necessary in d+ and d - line control the f ollowing d+ and d - resistors necessary for usb communication are installed : ? d+ p ull -u p resistor ? d+ and d - termination resistor s ( for hi - speed operations) ? d+ and d - output resistor s ( for full - spe ed operations) (2) 48mhz and 480mhz pll operations can be executed by selecting one of the three types of external clocks (12mhz/24mhz/48mhz). (3) 3.3v 1.5v regulator 1.5v core power is generated in this controller. in the system where a 3.3v interface power is used, this controller can be operated on a single power supply.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 11 of 142 jun 28,2013 2 register design of register table ? bit number : each register is connected to the 16- bit internal bus. odd address are from b15 to b8, and even address are from b7 to b0. ? status after reset : i ndicates the register initial status immediately after the reset operation. a hardware reset is the initialization status when the exter nal reset signal is entered from the rst_n pin. a usb bus reset is the initialization status when a usb bus reset is detected by the controller. significant points in the reset operation are mentioned in the n otes. " - " indicates the status of retained user setting s without any controller operations. "?" indicates the status when the value is not determined. ? software a ccess conditions : conditions when the register is accessed by the software. ? hardware a ccess conditions : conditions when the register is accessed by the controller during operations other than reset : r??read o nly w??write o nly r/w?read/write r(0)?"0" read o nly w(1)?"1" write o nly ? remarks : remarks and detail ed description item number. ? name : this is the bit symbol and bit name . ? funct ion : this is the description of the function. when there is no particular rejection, the value during r ead is the value written by the software or hardware. e xample : t he shaded portions are unassigned . fix to"0" . ? bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit symbol a bit b bit c bit ? hardware reset ? 0 0 0 usb bus reset ? 0 - - b it name function software hardware remarks 15 un assigned. fix to "0". 14 a bit aaa enabled 0: operati ons disabled 1: operations enabled r/w r 13 b bit bbb operation 0: low output 1: high output r w 12 c bit ccc control 0: ? ? ? ? ? ? ? 1: ? ? ? ? ? ? ? r(0) / w(1) r ? ? ? ? ? remarks
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 12 of 142 jun 28,2013 2.1 register list the controller register list is shown in table 2.1 . table 2 . 1 register list address symbol name index 00 syscfg0 system configuration control register 0 02 syscfg1 system configuration control register 1 04 syssts0 system con figuration status register 0 06 08 dvstctr0 device control register 0 0a 0c testmode test mode register 0e pincfg data pin configuration register 10 dma0cfg dma0 p in configuration register 12 dma1cfg dma1 p in configuration register 14 c fifo cfifo port register 16 18 d0fifo d0fifo port register 1a 1c d1fifo d1fifo port register 1e 20 cfifosel cfifo port selection register 22 cfifoctr cfifo port control register 24 26 28 d0fifosel d0fifo port selection registe r 2a d0fifoctr d0fifo port control register 2c d1fifosel d1fifo port selection register 2e d1fifoctr d1fifo port control register 30 intenb0 interrupt enable register 0 32 34 36 brdyenb brdy interrupt enable register 38 nrdyenb nrdy int errupt enable register 3a bempenb bemp interrupt enable register 3c sofcfg sof output configuration register 3e 40 intsts0 interrupt status register0 42 44 46 brdysts brdy interrupt status register 48 nrdysts nrdy interrupt status reg ister 4a bempsts bemp interrupt status register 4c frmnum frame nu mber register 4e ufrmnum microframe number register 50 usbaddr usb address register 52 54 usbreq usb request type register 56 usbval usb request value register 58 usbindx u sb request index register 5a usbleng usb request length register 5c dcpcfg dcp configuration register 5e dcpmaxp dcp max imum packet size register 60 dcpctr dcp control register 62 64 pipesel pipe window selection register 66 68 pipecfg pipe configuration register 6a pipebuf pipe buffer specification register 6c pipemaxp pipe max imum packet size register 6e pipeperi pipe period control register
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 13 of 142 jun 28,2013 address symbol name index 70 pipe1ctr pipe1 control register 72 pipe2ctr pipe2 control register 74 pipe3ctr p ipe3 control register 76 pipe4ctr pipe4 control register 78 pipe5ctr pipe5 control register 7a pipe6ctr pipe6 control register 7c pipe7ctr pipe7 control register 7e pipe8ctr pipe8 control register 80 pipe9ctr pipe9 control register 82 - 8e 90 pipe1tre pipe1 transaction counter enabled register 92 pipe1trn pipe1 transaction counter register 94 pipe2tre pipe2 transaction counter enabled register 96 pipe2trn pipe2 transaction counter register 98 pipe3tre pipe3 transaction counter enable d register 9a pipe3trn pipe3 transaction counter register 9c pipe4tre pipe4 transaction counter enabled register 9e pipe4trn pipe4 transaction counter register a0 pipe5tre pipe5 transaction counter enabled register a2 pipe5trn pipe5 transaction c ounter register a4 - e 6 nothing is assigned to the shaded portions. do not access.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 14 of 142 jun 28,2013 2.2 bit symbol list a list of controller bit symbols is shown in table 2.2 . table 2 . 2 bit s ymbol list addr register name odd numbers even numbers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 syscfg0 xtal xcke pllc scke hse dcfm dprpu usbe 02 syscfg1 cntflg pcsdis lpsme 04 syssts0 lnst 06 08 dvstctr0 wkup rhst 0a 0c test mode utst 0e pincfg ldrv inta 10 dma0cfg dreqa burst dacka dform denda pktm dende obus 12 dma1cfg dreqa burst dacka dform denda pktm dende obus 14 cf ifo cfport 16 18 d0fifo d0fport 1a 1c d1fifo d1fiport 1e 20 cfifosel rcnt rew mbw bigend isel curpipe 22 cfifoctr bval bclr frdy dtln 24 26 28 d0fifosel rcnt rew dclrm dreqe mbw bigend curpipe 2a d0fifoctr bval bclr frdy dtln 2c d1fifosel rcnt rew dclrm dreqe mbw bigend curpipe 2e d1fifoctr bval bclr frdy dtln 30 intenb0 vbse rsme sofe dvse ctre bempe nrdye brdye 32 34 36 brdyenb pipebrdye 38 nrdyenb pipenrdye 3a bempenb pipebempe 3c sofcfg brdym intl edgests sofm 3e 40 intsts0 vbint resm sofr dvst ctrt bemp nrdy brdy vbsts dvsq valid ctsq 42 44 46 brdysts pipebrdy 48 nrdysts pipenrdy 4a bempsts pipebemp 4c frmnum ovrn crce frnm 4e ufrmnum ufrnm 50 usbaddr usbaddr 52 54 usbreq brequest bmreques ttype 56 usbval wvalue 58 usbindx windex 5a usbleng wlength 5c dcpcfg cntmd shtnak 5e dcpmaxp mxps 60 dcpctr bsts sqclr sqset sqmon pbusy ccpl pid 62 64 pipesel pipesel 66 68 pipecfg type bfre dblb cntmd shtnak dir epnum 6a pipebuf bufsize bufnmb 6c pipemaxp mxps
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 15 of 142 jun 28,2013 addr register name odd numbers even numbers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6e pipeperi ifis iitv 70 pipe1ctr bsts inbufm atrepm aclrm sqclr sqset sqmon pbusy pid 72 pipe2ctr bsts inbufm atrepm aclrm sqclr sqset sqmon pbusy pid 74 pipe3ctr bsts inbufm atrepm aclrm sqclr sqset sqmon pbusy pid 76 pipe4ctr bsts inbufm atrepm aclrm sqclr sqset sqmon pbusy pid 78 pipe5ctr bsts inbufm atrepm aclrm sqclr sqset sqmon pbusy pid 7a pipe6ctr b sts aclrm sqclr sqset sqmon pbusy pid 7c pipe7ctr bsts aclrm sqclr sqset sqmon pbusy pid 7e pipe8ctr bsts aclrm sqclr sqset sqmon pbusy pid 80 pipe9ctr bsts aclrm sqclr sqset sqmon pbusy pid 82 - 8e 90 pi pe1tre trenb trclr 92 pipe1trn trncnt 94 pipe2tre trenb trclr 96 pipe2trn trncnt 98 pipe3tre trenb trclr 9a pipe3trn trncnt 9c pipe4tre trenb trclr 9e pipe4trn trncnt a0 pipe5tr e trenb t rclr a2 pipe 5 trn trncnt a4 - e 6
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 16 of 142 jun 28,2013 2.3 system configuration control ? system configuration control register 0 (syscfg0) r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 17 of 142 jun 28,2013 2.3.1 xin c lock s election b it ( xtal ) in this bit, write the value corresponding to the quartz crystal or oscillator connected to the xin pin. this controller deter mines the increasing multiples of 48mhz pll according to the s etup value of this bit. this bit is set immediately after a hardware reset. do not modify it during controller operations. 2.3.2 oscillation b uffer e nable b it ( xcke ) write " 1" to this bit to enable the oscillation buffer operations of this controller. write "0" to disable the oscillation buffer operations. do not write "xcke=0" for the time (time when "cntflg=1" is displayed) when clock restoration process is carried out by the controller. write "x cke=1" to end the clock restoration process. 2.3.3 48mhz pll o perations e nabled b it ( pllc ) write "1" to this bit to enable this controller ? s 48mhz pll operations. write "0" to disable them . 2.3.4 usb b lock c lock e nabled b it ( scke ) write "1" to this bit to enable th is controller ? s clock supply to the usb block. write "0" to disable it . w hen "0" is written to this bit, t he registers that can be written to are shown in table 2.3 . other registers cannot be written. each regist er can be read when "0" is written to this bit . table 2 . 3 list of r egisters t hat c an b e w ritten by the s oftware w hen " scke =0 " address register name 00h syscfg0 02h syscfg1 0eh pincfg 2.3.5 hi - speed o perations e nabled b it ( hse ) write "1" to this bit to enable hi - speed operations. when "hse=1" is written , this controller operates hi - speed or full - speed depending on the r eset handshake result. when "hse=0" is written , the controller executes full - speed operations . when "hse=1" is written , the controller executes r eset h andshake p rotocol and, depending on the result, hi - speed or full - speed operations are executed automatically. t his bit can be modified when "dprpu=0". 2.3.6 controller function selection bit (dcfm) set this bit to specify the usb controller function on or off . this bit can be modified when "dprpu=0". s ee section 2.11.1.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 18 of 142 jun 28,2013 2.3.7 d+ line resistance control ( dprpu ) settings related to usb data bus resistance is given in table 2 . 4 . select usb data bus resistance in dprpu bit s . table 2 . 4 usb data bus resistance control write contents usb data bus resistance control dprpu d+ line remarks 1 pull - u p set d+ line when it is a pull - up . 0 open set d+ line when it release s a pull - up. if "1" is written to this bit , the controller pulls up the d+ line to 3.3v, and can notify the usb host of an " a ttach". the controller cancels the d+ line p ull - u p if the bit setting is changed from "1" t o "0", and the status for the usb h ost can be shown as detached . 2.3.8 usb b lock o perations e nabled b it ( usbe ) t h is controller? s usb block operations can be enabled/disabled by writing to this bit . if the bit is modified from "usbe=1" to "usbe=0", the control ler initializes the bits shown in table 2.5 . table 2 . 5 list of registers i nitialized when writing " usbe=0" register n ame bit name remark syssts0 lnst dvstctr0 rhs t intsts0 dvsq usbaddr usbaddr usbreq brequest bmrequesttype usbval wvalue usbindx windex usbleng wlength this bit can be modified when "scke=1".
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 19 of 142 jun 28,2013 ? system configuration control register 1 [syscfg1] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cntflg pcsdis lpsme hse ? ? ? 0 ? ? 0 0 0 ? ? ? ? ? ? ? ? ? - ? ? - - - ? ? ? ? ? ? bit name function software hardware remarks 15 - 13 un assigned. fix to "0 " . 12 cntflg auto clock monitor displays whether auto clock s etup process is currently being executed. 0: auto clock process complete or clock stopped 1: a uto clock process ing r w 11 - 10 un assigned. fix to "0 " . 9 p csdis r est oration from low power sleep mode by cs n disabled specifies whether restoration from l ow power sleep mode is possible due to fall in cs_n. 0: restoration en abled due to cs_n 1: restoration disa bled due to cs_n r/w r 8 lpsme low power sleep mode enabled specifies whether the controller can shift to l ow power sleep mode when the clock is being stopped. 0: low power sleep mode disabled 1: low power sleep mode enabled r/w r 7 - 0 un assigned. fix to "0 " . remarks none 2.3.9 auto c lock m onitoring b it ( cntflg ) this bit sets "1" when the clock restoration process is being executed by the controller. this bit is modified from "0" to "1" when the clock restoration process by the controller is started, and after the clock is restored and when "scke=1" , "1" is modified t o "0". 2.3.10 cs_n restoration disabled b it (pcsdis) this bit enables or disables the falling edge of cs_n as an event to shift the controller from low power sleep mode to normal status. refer to table 2 . 6 for the difference in restorat ion events according to the s etup value of this bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 20 of 142 jun 28,2013 2.3.11 low p ower s leep m ode e nabled b it (lpsme) this controller enters l ow p ower s leep mode when the oscillation buffer is stopped ("xcke=0" setting) and when "lpsme=1". t he standby power can be further reduce d compared to w hen "lpsme=0" and in the o scillation b uffer s topped mode . the two types of events that help this controller restore to normal clock operatin g status from the l ow power s leep mode , which was caused by "lpsme=1" and "xcke=0", are given below . table 2 . 6 restoration event from low power sleep mode ("lpsme=1" and "xcke=0") conditions restoration e vents if writing "pcsdis=0" (1) resm interrupt detection if writing "rsme=1" (2) vbint interrupt dete ction if writing "vbse=1" (3) cs_n signal assert by dummy reading from cpu if writing "pcsdis=1" (1) resm interrupt detection if writing "rsme=1" (2) vbint interrupt detection if writing "vbse=1" write "lpsme=1" when "xcke=1". when writing "lpsme=1", wr iting "xcke=0 " makes this controller enter low power sleep mode, and access to the controller is disabled for 10s. therefore , exit from l ow power sleep mode with a dummy reading from the cpu after at least 10s have elapsed after writing "xcke=0". when the controller is shifted to l ow power sleep mode , the value in the fifo buffe r is lost. while using the controller with "lpsme=1", read the fifo contents or clear the fifo buffer before writing "xcke=0".
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 21 of 142 jun 28,2013 2.4 system configuration status ? system configuration status register 0 [syssts0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lnst ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit name function software hardware remarks 15 - 2 un assigned. fix to "0". 1 -0 lnst usb data line interface monitor sets the usb line status ? refer to the d etail ed explanation. r w remarks none 2.4.1 line s tatus m onitor b it (lnst) usb data bus line status table of the controller is shown in table 2.7 . the controller monitors the usb data bus line status (d+ and d - line ) in the syssts0 register lnst bit . refer to this lnst bit after the " a ttach" process ( write "dprpu=1"). table 2 . 7 usb data bus line status lnst [1] lnst [0] full - speed operations hi - speed operations chirp o perations 0 0 se0 squelch squelch 0 1 j - state unsquelch chirp j 1 0 k - state invalid chirp k 1 1 se1 invalid invalid chirp: reset h andshake protocol being executed in hi - speed operations enabled status (hse="1") squelch: se0 or i dle status unsquelch: hi - speed j state or hi - speed k state chirp j: chirp j - state chirp k: chirp k - state
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 22 of 142 jun 28,2013 2.5 usb signal control ? device state control register 0 [dvstctr0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wkup rhst ? ? ? ? 0 ? 0 0 0 ? ? ? ? 0 ? - - - bit name function software hardware remarks 15 - 9 unassigned . fix to "0". 8 wkup wakeup output specifies whether the remote wakeup ( r esume signal output) is disabled / enabled 0: remote wakeup signal not output 1: remote wakeup sig nal output r/w(1) r/w(0) 7 - 3 un assigned. fix to "0". 2 -0 rhst r eset handshake displays the usb port reset handshake status. ? refer to the detailed explanation. r w remarks none
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 23 of 142 jun 28,2013 2.5.1 remote w akeu p ( r esume s ignal o utput) e nabled/ d isabled b it (wkup) if "1 " is written to this bit , the controller outputs the remote wakeup signal to the usb bus. the controller manages the output time of the remote wakeup signal. if the software writes "1" to the wkup bit, the controller outputs a "k - state" of 10ms and then ch anges the setting to "wkup=0". according to the usb specification revision 2.0 , the usb bus idle status should be maintained for at least 5ms until the remote wakeup signal is sent. therefore, the controller outputs a k-s tate after waiting for 2ms, althoug h "wkup=1" is written immediately after detecting the s uspend status. write "1" to the wkup bit only when the device state is s uspend ("dvsq=1xx") and when the remote wakeup is enabled from the usb h ost. do not stop the internal clock when "1" is written to the wkup bit, irrespective of the s uspend status ( write "wkup=1" in the "scke=1" status). 2.5.2 r eset h andshake s tatus b it (rhst) the controller set s the result of the r eset h andshake in this bit. the result s of r eset h andshake are listed in table 2.8 . table 2 . 8 usb d ata b us l ine s tatus bus s tatus rhst bit v alue when p owered or during d isconnect 000 during r eset h andshake 100 when connecting to full - speed 010 w hen connecting to hi - speed 011 when "hse=1" is set, the bit shows "100" when the controller detects a usb bus reset. the controller then outputs chirp k, and this bit shows "011" when chirp jk is detected three times from the usb h ost. after chirp k is output, if it is not set to hi - speed within 2.5ms, the bit shows "010". when "hse=0" is set, the bit shows "010" when the controller detects the usb bus reset. a dvst interrupt is generated when the rhst bit is set to "0101" or "011" after the usb bus reset is detected by the controller.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 24 of 142 jun 28,2013 2.6 test mode ? test mode register [testmode] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 utst ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? - - - - bit name function software hardware remarks 15 - 4 un assigned. fix it to "0". 3 -0 ut st test mode ? refer to detail ed description. r/w r remarks none 2.6.1 test m ode b it (utst) the controller writes the value to this bit to output the usb test signal during hi - speed operations. the t est mode operations of the controller are given in table 2.9 . table 2 . 9 test mode operations test mode utst bit settings normal operations 0000 test_j 0001 test_k 0010 test_se0_nak 0011 test_packet 0100 reserved 0101 - 1 111 w rite this bit according to the s et f eature request from the usb h ost during hi - speed communication. the controller does not move to s uspend status if " 0001 " ~ " 0100 " is written to the bit . to perform normal usb communications after the test mode is set, execute a hardware reset first.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 25 of 142 jun 28,2013 2.7 bus interface control ? data pin configuration register [pincfg] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ldrv inta 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 - ? ? ? ? ? ? ? ? ? ? ? ? ? ? - bit name function software hardware remarks 15 ldrv output pin dr ive current control 0: when vif=1.6 - 2.0v 1: when vif=2.7 - 3.6v r/w r 14 - 1 un assigned. fix to "0". 0 inta int_n active settings sets a ctive of interrupt output from int_n pin. 0: low a ctive 1: high a ctive r/w r remarks none 2.7.1 output pin drive current co ntrol bit (ldrv) for this bit, write the value that matches the vif power supply . the f ollowing are the output pins to be controlled using the drive current according to this bit : sd7 -0 , d15 -0 , int_n , dreqx_n , dendx_n and sof_n pin s. write to this bit af ter re setting the hardware and do not modify it during controller operations. 2.7.2 int_n a ctive s etting b it (inta) set the a ctive (low/high) for interrupt output from int_n that matches the interrupt input specifications of the cpu for control. write to this bit after re setting the hardware, and do not modify it during controller operations.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 26 of 142 jun 28,2013 the dma0cfg register is for the dma0 interface input/output pin and to control the d0fifo port. the dma1cfg register is for the dma1 interface input/output pin and to con trol the d1fifo port. ? dma0 pin configuration register [dma0cfg] ? dma1 pin configuration register [dma1cfg] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dreqa burst dacka dform denda pktm dende obus ? 0 0 ? ? 0 0 0 0 0 0 0 ? 0 ? ? ? - - ? ? - - - - - - - ? - ? ? bit name function software hardware remarks 15 un assigned. fix to "0". 14 dreqa dreqx_n signal polarity selection indicates the a ctive of the dreqx_n pin. 0: low a ctive 1: high a ctive r/w r 13 burst burst m ode for dxfifo, specifies whether to access by cycle steal transfer or by burst transfer. 0: cycle steal transfer 1: burst transfer r/w r 12 - 11 un assigned. fix to "0". 10 dacka dackx_n signal polarity selection specifies a ctive of the dackx_n pin. 0: lo w a ctive 1: high a ctive r/w r 9 -7 dform dma transfer signal selection specifies the control signal while accessing the fifo buffer by dma. 000: use a ddress signal+rd_n/wrx_n signal (cpu bus) 010: use dackx_n+rd_n/wrx_n signal (cpu bus) 011: use dackx_n s ignal only (cpu bus) 100: use dackx_n signal (split bus) 001, 101, 110 and 111: reserved r/w r 6 denda dendx_n signal polarity selection specifies a ctive of dendx_n pin 0: low a ctive 1: high a ctive r/w r 5 pktm dend output packet mode specifies dend ou tput timing. 0: assert dendx_n signal in the transfer unit 1: assert dendx_n signal for every data transfer of the given buffer size r/w r 4 dende dendx_n signal enabled enables the input/output of dendx_n signal. 0: dendx_n signal disabled (hi - z output) 1: dendx_n signal enabled r/w r 3 un assigned. fix to "0". 2 obus obus operations disabled disables the obus operations. 0: obus mode enabled 1: obus mode disabled r/w r 1 - 0 un assigned. fix to "0". remarks none
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 27 of 142 jun 28,2013 2.7.3 dma s ignal c ontrol if transferring da ta using the dma interface, use the dmaxcfg register ? s burst bit, pktm bit, dende bit, and obus bit to select the dma interface operation ( a ssert/negate of dreqx_n / dendx_n signal and dma transfer mode settings) that is configured to the user system . the d ma signal is valid for access to the fifo buffer assigned to the pipe selected by the dxfifosel register curpipe bit (to be mentioned later ) . when the status of the pipe fifo buffer changes to buffer ready ( brdy ) status, this controller asserts the dreqx_n signal if " dreqe =1" . 2.7.4 dreqx_n s ignal p olarity s election b it (dreqa) set a ctive of dreqx_n pin in this bit. for the fifo port, write to this bit when "curpipe=000". 2.7.5 burst m ode b it (burst) when the dma controller executes a cycle steal transfer for dxfif o, write "0" to this bit . the controller negates a dreqx_n signal for access to one word or one byte. when the dma controller executes a burst transfer for dxfifo, write "1" to this bit . the controller negates the dreqx_n signal for accessing the last on e word or one byte of fifo buffer. do not modify the bit during pipe communication operation s . 2.7.6 dackx_n s ignal p olarity s election b it (dacka) in this bit, set a ctive the dackx_n pin. for the fifo port, write to this bit when " curpipe = 000 " . 2.7.7 dma t ransfe r s ignal s election b it (dform) in this bit, set the control signal while accessing the fifo buffer with the dma controller. for the fifo port, write to this bit when " curpipe = 000 " 2.7.8 dendx_n s ignal p olarity s election b it (denda) in this bit, set a ctive the dendx_n pin. for the fifo port, write to this bit when " curpipe = 000 " . 2.7.9 dend o utput p acket m ode b it (pktm) write the dend output timing in this bit. when "0" is written to this bit , the controller asserts the dendx_n signal when any of the following co nditions are fulfilled : (1) during the last r ead a ccess while reading the short packet data (2) during the last r ead a ccess while reading the data completed at the transaction counter ( trncnt ) (3) if a z ero -l ength packet is received when the fifo buffer is empty when "1" is written to this bit , the controller asserts a dendx_n output for every data transfer of the given fifo buffer size. for the fifo port, write to this bit when " curpipe = 000 " .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 28 of 142 jun 28,2013 2.7.10 input/output e nabled b it of the dendx_n s ignal (dende) set i/o enabled/disabled for the dendx_n pin in this bit. for the fifo port, write to this bit when " curpipe = 000 " . 2.7.11 obus o peration d isabled b it (obus) in this bit, write obus operations to be enabled / disabled. when "0" is written to this bit , the sd7 - 0 of the split bus and dend is always input/output enabled" . when " 1 " is written to this bit , t he sd7 - 0 of the split bus and dendx_n are are e nabled only when dackx_n is active. while commonly using d0fifo and d1fifo in the split bus, write "1" to all the ob us bits.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 29 of 142 jun 28,2013 2.8 fifo port ? cfifo port register [cfifo] ? d0 fifo port register [ d0 fifo] ? d1fifo port register [d1fifo] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fifoport 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - bit name function software hardware remarks 15-0 fifoport fifo port reads the received data from the fifo buffer by accessing this bit, or writes the being transmitted data to the fifo buffer. r/w r/w remarks none 2.8.1 fifo p ort c ontrol the rx/tx buffer me mory of this controller is made up of a fifo structure (fifo buffer). use the fifo port register to access the fifo buffer. the cfifo port, d0fifo port and d1fifo port are the types of fifo ports. each fifo port consists of port registers ( cfifo , d0fifo and d1fifo ) that read or write the data from or to the fifo buffer, registers ( cfifosel , d0fifosel and d1fifosel ) that select the pi pes assigned to fifo port, and control registers ( cfifoctr, d0fifoctr and d1fifoctr ). the features of each fifo port are as f ollows: (1) access the fifo buffer for dcp using the cfifo port. (2) the fifo buffer access using the dma transfer can be done through the dxfifo port. (3) dxfifo port access by the cpu is also possible. (4) while using functions specific to the fifo port, the pipe number (s elected pipe) to be written to the curpipe bit cannot be modified ( s ignal input/output to the pin related to dma, etc . ). (5) registers containing the fifo port do not affect the other fifo ports. (6) do not assign the same pipe to separate fifo ports. (7) in the fi fo buffer status, there are two types of access rights: one assigned to the cpu , and the other to sie. access from the cpu is not possible when sie has the rights to access the buffer memory.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 30 of 142 jun 28,2013 2.8.2 fifo p ort b it ( cfifo, d0fifo and d1fifo ) the controller acces ses the fifo buffer assigned to the pipe number written to the curpipe bit of various selected registers ( cfifosel, d0fifosel or d1fifosel ). access to this register is possible only when the frd y bit of each control register ( cfifoctr , d0fifoctr or d1fif octr ) s how s "1" (or while this controller asserts dreqx_n) . the valid bits of this register differ according to the s etup value of the mbw and bigend bits. the valid bits are shown in table 2.10 . table 2 . 10 fifo port valid bit s mbw setup v alue bigend setup v alue b15 - b8 b7 - b0 0 0 invalid n+0 byte 0 1 n+0 byte invalid 1 0 n+1 byte n+0 byte 1 1 n+0 byte n+1 byte if writing " mbw =0", the n+0 byte as shown in table 2.10 can be accessed. during read, access the 16 - bit width for addresses 1 4 h, 18 h and 1 c h and use them as 8 - bit data on n+0 byte as shown in table 2.10. during write, access the 16 - bit width for addresses 14h, 18h and 1c h ( a ccess by asserting both wr0_n and wr1_n. in this case, the controller ignores the n+1 byte as shown in table 2.10 ), or access the 8 - bit width for addresses 14h, 18h and 1c h (a ssert only wr0_n). if writing " mbw =1", the n+0 byte shown in table 2.10 can be accessed. during read, access the 16 - bit width for addresses 14h, 18h and 1 c h. during write, access the 16 - bit width for ad dresses 14h, 18h and 1c h ( a ccess by asserting wr0_n and wr1_n). do not access the address for 15h, 19h and 1 d h.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 31 of 142 jun 28,2013 ? fifo port selection register [cfifosel] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rcnt rew mbw bigend isel curpipe 0 0 ? ? ? 0 ? 0 ? ? 0 ? 0 0 0 0 - - ? ? ? - ? - ? ? - ? - - - - bit name function software hardware remarks 15 rcnt read count mode specify r ead mode of cfifoctr dtln. 0: dtln bit clear by read of all the data received 1: dtln bit count down for read of all the received data r/w r 14 rew buffer pointer rewind specify "1" while rewinding the buffer pointer. 0: do not rewind the buffer pointer 1: rewind buffer pointer r(0)/w r /w(0) 13 - 11 un assigned. fix to "0". 10 mbw cfifo port access bit width speci fy the cfifo port access bit width . 0: 8 - bit width 1: 16 - bit width r/w r 9 un assigned. fix to "0". 8 bigend fifo port endian control specify the cfifo port byte e ndian . 0: little e ndian 1: big e ndian r/w r 7 - 6 un assigned. fix to "0". 5 isel access di rection of the fifo port when dcp is selected specify access direction of the fifo port when dcp is selected in curpipe bit . 0: this selects read from the buffer memory 1: this selects write to the buffer memory r/w r 4 - 3 un assigned. fix to "0". 2 -0 cur pipe fifo port access pipe specification specify the pipe number to access the cfifo port. 0000: dcp 0001: p ipe 1 0010: p ipe 2 1000: p ipe 8 1001: p ipe 9 r/w r remarks none
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 32 of 142 jun 28,2013 2.8.3 read c ount m ode (rcnt) when "0" is written to this bit , if all reception data of the fifo buffer assigned to the pipe specified in the curpipe bit is read (when the data is read on one side of a double buffer ), the controller clears the cfifoctr register dtln bit t o "0". when " 1 " is written to this bit , the controller counts the cfi foctr register dtln bit whenever the data received from the fifo buffer assigned to the specified bit is read. 2.8.4 buffer pointer rewind (rew) when the selection pipe is rece iving , if "1" is written to this bit during the fifo buffer read, the initial data of the fifo buffer can be read ( for a double buffer, the initial data on one side can be read again during the read process) . when the software writes "1" to this bit, the controller again writes "0" to this bit. do not modify the "rew=1" setting s and the c urpipe bit settings at the same time . first confirm that "frdy=1" and then write "rew=1". use the bcl r bit while rewriting the initial data of the fifo buffer for the transmission pipe . 2.8.5 cfifo port access bit width (mbw) in this bit, set the cfifo port a ccess bit width. when the pipe specified in the curpipe bit is rece iving , if read is started after writing "1" to this bit, modify the mbw bit from "1" to "0" only after all the data is read. when the dtln bit is an odd number , write "mbw=0" and read wit h the variable having an 8 - bit length, or read with a 16- bit maintaining "mbw=1" , delete the excess byte, and then read the last byte. when the specified pipe is rece iving , set the curpipe bit and mbw bit simultaneously. when the the specified pipe is transmi tting , to start writing the data having an odd number of bytes by writing "1" to this bit , write "mbw=0" and write with the variable having a 16- bit length ( r efer to 2.8.2 for the data to be written) , or write with the variable having an 8 - bit length maintaining "mbw=1", and then write the last byte ( w rite with the wr0_n strobe if "bigend=0", and with the wr1_n strobe if "bigend=1"). 2.8.6 control bit of cfifo port byte e ndian (bigend) in this bit, write the cf ifo port byte e ndian . refer to 2.8.2 for details. 2.8.7 fifo port access direction specification bit when selecting dcp (isel) to change this bit when the specified pipe is dcp, first write the data to this bit and t hen read it. proceed to the next process after checking if the written values match with the read values. when the settings of this bit are modified during access to the fifo buffer, access up to then is saved. access to the buffer can be continued after rewriting the settings. write to this bit and the curpipe bit simultaneously. 2.8.8 fifo port access byte specification bit (curpipe) write the pipe number for the data to be read or written through the cfifo port. wh en modifying this bit, first write the data ? 0 ? and then write specified pipe number. c heck that the written values and the read values match , and then proceed to the next process. do not write to the same pipe to curpipe of cfifosel , d0fifosel , and d1fifosel registers . when the settings of t his bit are modified during access to the fifo buffer, access up to then is saved. access to the
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 33 of 142 jun 28,2013 buffer can be continued after rewriting the settings.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 34 of 142 jun 28,2013 ? d0fifo port selection register [d0fifosel] ? d1fifo port selection register [d1fifosel] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rcnt rew dclrm dreqe mbw bigend curpipe 0 0 0 0 ? 0 ? 0 ? ? ? ? 0 0 0 0 - - - - ? - ? - ? ? ? ? - - - - bit name function software hardware remarks 15 rcnt read c ount mode specify the read mode of dx_fifoctr dtln . 0: the dtln bit is cleared when all the reception data has been read 1: the dtln bit is decremented when the reception data is read r/w r 14 rew buffer pointer rewind specify "1" to rewind the buffer pointer. 0: invalid 1: the buffer pointer is rewound r(0)/w r /w(0) 13 dclrm this is the a uto b uffer m emory clear mode accessed after the data for the specified pipe has been read. specify whether auto buffer memory clear is disabled/enabled after the data for the specified pipe has been read. 0: a uto b uffer c lear mode is disabled 1: auto b uffer c lear mode is enabled r/w r 12 dreqe dreq signal output enabled specify whether the dr eq signal is disabled/enabled. 0: output is disabled 1: output is enabled r/w r 11 un assigned. fix to "0". 10 mbw fifo port access bit width specify the fifo port access bit width. 0: 8 - bit width 1: 16 - bit width r/w r 9 nothing is assigned. fix to "0" . 8 bigend fifo port endian control specify the byte e ndian of each fifo port. 0: little e ndian 1: big e ndian r/w r 7 - 4 un assigned. fix to "0". 3 -0 curpipe fifo port access pipe specification 0000: no specification 0001: pipe1 0010: p ipe 2 1000: p ip e 8 1001: p ipe 9 r/w r remarks none 2.8.9 read count mode (rcnt) when " 0 " is written to this bit , if all reception data of the fifo buffer assigned to the pipe specified in the curpipe bit is read ( for a double buffer, when the data on one side is read), the c ontroller clears the dxfifoctr register dtln bit to "0 " . when "1" is written to this bit , the controller counts the dxfifoctr register dtln bits each time during the reception data read of the fifo buffer assigned to the specified pipe . write "0" to th is bit to access dxfifo by writing "1" to the bfre bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 35 of 142 jun 28,2013 2.8.10 buffer pointer rewind (rew) when the selection pipe is rece iving , if "1" is written to this bit during the fifo buffer read, the initial data of the fifo buffer can be read ( for a double buffer, du ring the read process, the initial data on one side can be read again). when the software writes "1" to this bit, the controller again writes "0" to this bit . do not modify the "rew=1" settings and the curpipe bit settings as the same time . first confirm the "frdy=1" and then write "rew=1". use the blcr bit while rewriting the initial data of the fifo buffer for the transmission pipe . 2.8.11 auto fifo buffer clear disabled/enabled bit (dclrm) after read ing the specified pipe data, set disabled/enabled for the auto fifo buffer clear. when "1" is written to this bit , the controller executes a " bclr=1" process of the fifo buffer if a z ero -l ength packet is received when the fifo buffer assigned to the specified pipe is empty, or when the short packet reception dat a is read if writing " bfre=1". if "brdym=1" is written when using this controller, make sure to write "0 " to this bit . 2.8.12 dreqx_n output disabled/enabled bit (dreqe) write this bit so that the dxreq_n signal output can be disable d /enable d . when the dxreq _n signal output is enabled, write "1" to this bit after writing to the curpipe bit. write "0 " to this bit and then modify the curpipe bit. 2.8.13 dxfifo port access bit width (mbw) write the dxfifo port access bit width in this bit . refer to 2.8.5 for details. 2.8.14 control bit of dxfifo port byte e ndian (bigend) write the dxfifo port byte e ndian in this bit . r efer to 2.8.2 for details. 2.8.15 fifo port access pipe specification bit ( curpipe) write the pipe number for the data to be read or written through the dxfifo port. to modify this bit, first write the data to this bit and then read it . c heck if the write value matches the read value and then proceed to the next process. do n ot write the same pipe to the cfifosel , d0fifosel , and d1fifosel registers? curpipe . when thi s bit is modified during access to the fifo buffer, access up to then is saved. access to the buffer can be continued after rewriting.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 36 of 142 jun 28,2013 ? cfifo port control register [cfifoctr] ? d0fifo port control register [d0fifoctr] ? d1fifo port control register [d1fifoctr] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bval bclr frdy dtln 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 - - - ? - - - - - - - - - - - - bit name function software hardware remarks 15 bval b uffer memory valid flag specify "1" when write of the fifo buffer ends on the cpu side of pipe specified in curpipe. 0: invalid 1: writing ended r/w(1) r/w 14 bclr cpu buffer clear specify "1" to clear the fifo buffer on the cpu side of the pipe . 0: invalid 1: clears the cpu buffer memory r(0)/w(1) r /w(0) 13 frdy fifo p ort r eady indicates whether the fifo port can be accessed. 0: fifo port access disabled 1: fifo port access enabled r w 12 un assigned. fix to "0". 11-0 dtln reception d ata l ength displays reception data length of fifo buffer for corresponding pipe. r w remarks none 2.8.16 buffer memory valid flag (bval) when the pipe specified in the curpipe bit is transmi tting , write "1" to this bit in the cases below . the controller writes the fifo buffer from the cpu side to the sie side to make transmission possible. (1) to transmit the short packet, write "1" to this bit after the data is written. (2) to transmit a z ero -l ength packet, write "1" to this bit before writing the data to fifo. (3) for the pipe in continuous transfer mode, write "1" to this bit after writing the maximum packet size in multiples of natural integers and data less than the buffer size. if the data of the maximum packet size is written for the pipe in continuous transfer mode, the controller writes "1" to this bit, sets the cpu fifo buffer to the sie side, and changes to transmission possible status. when the specified pipe is tr ansmi tting , if "1" is written simultaneously to the bval and bclr bit s , the controller clears the data written previously and changes the status of the z ero -l ength packet to t ransmission p ossible. when the controller indicates "frdy=1", write "1" to this bit. when the specified pipe is rece iving , do not write "1" to this bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 37 of 142 jun 28,2013 2.8.17 cpu buffer clear bit (bclr) if "1" is written to this bit , the controller clears the fifo buffer on the cpu side from the fifo buffers assigned to the specified pipe . when the setting of the fifo buffer assigned to the specified pipe is a d ouble buffer, the controller clears the fifo buffer only on one side, though the buffers on both sides can be read. when the specified pipe is dcp, the controller clears the fifo buffer whe n "bclr=1", irrespective of the cpu or sie side. to clear the buffer on the sie side, write "bclr=1" after writing "nak" to the pid bit. if the specified pipe is not dcp, write "1" to this bit when the controller sets "frdy=1". 2.8.18 fifo port ready bit (frdy ) in this bit, the controller shows if access is possible to the fifo port from the cpu (dmac). in the following cases, the controller s et s "frdy=1", but cannot read the data from the fifo port since the data is not available. in these cases, write "bclr =1", clear the fifo buffer, and then change the status to data send/receive. (1) if a zero - length packet is received when the fifo buffer assigned to the specified pipe is empty. (2) if "bfre=1" is written , when the short packet is received and the data is read. 2.8.19 reception data length bit (dtln) the controller s et s the reception data length in this bit. the value of this bit changes according to the s etup value of the rcnt bit during the fifo buffer read. (1) when "rcnt=0": the controller s et s the reception data length in this bit until the cpu (dmac) reads all the reception data on one side of the fifo buffer. when "bfre=1", the controller holds the reception data length until "bclr=1", although the data is read. (2) when "rcnt=1": the controller counts the dtln bit display during each data read ( c ounts down by -1 when "mbw=0", and by -2 when "mbw=1") . when the data on one side of the fifo buffer is read, the controller set s "dtln=0". however, when the double buffer is set , and when data is received in the fifo buffer on one side before reading the reception data on other fifo buffer, the reception data on one side is set in the dtln bit when read on the first side is being completed. when "rcnt=1", while reading the value of this bit during fifo buffer re ad, the controller set s the updated value of this bit up to150ns after the read cycle of the fifo port.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 38 of 142 jun 28,2013 2.9 interrupts e nabled ? interrupt enabled register 0 [intenb0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vbse rsme sofe dvse ctre bempe nrdy e brdye 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? - - - - - - - - ? ? ? ? ? ? ? ? bit name function software hardware remarks 15 vbse vbus interrupts enabled specify int_n disable d /enable d while detecting vbint interrupts. 0: interrupt output disabled 1 : interrupt output enabled r/w r 14 rsme resume interrupts enabled specify int_n assert disable d /enable d while detecting resm interrupt. 0: interrupt output disabled 1: interrupt output enabled r/w r 13 sofe frame number update interrupts enabled speci fy int_n assert disable d /enable d while detecting sof interrupt. 0: interrupt output disabled 1: interrupt output enabled r/w r 12 dvse device state transition interrupts enabled specify i nt _n assert disable d /enable d while detecting dvst interrupt. 0: int errupt output disabled 1: interrupt output enabled r/w r 11 ctre control transfer stage transition interrupts enabled specify i nt _n assert disable d /enable d while detecting ctrt interrupt. 0: interrupt output disabled 1: interrupt output enabled r/w r 1 0 bempe buffer e mpty interrupts enabled specify i nt _n assert disable d /enable d while detecting bemp interrupt. 0: interrupt output disabled 1: interrupt output enabled r/w r 9 nrdye buffer n ot r eady response interrupts enabled specify i nt _n assert disable d /enable d while detecting nrdy interrupt. 0: interrupt output disabled 1: interrupt output enabled r/w r 8 brdye buffer r eady interrupts enabled specify i nt _n assert disable d /enable d while detecting brdy interrupt. 0: interrupt output disabled 1: interru pt output enabled r/w r 7 - 0 un assigned. fix to "0". remarks 2.9.1 interrupt enabled registers 0 (intenb0) when the controller detects the interrupt corresponding to the bit for which the software has written "1" to the register, the controller asserts an in terrupt from the int_n pin. the controller set s "1" to this status bit corresponding to the intsts0 register when the detection conditions of each interrupt factor are satisfied, irrespective of the s etup value of the register (interrupt notification dis abled/enabled). when the status bit of the intsts0 register corresponding to each interrupt factor are set to "1", if the software modifies the interrupt enabled bit corresponding to the register from "0" to "1", the controller asserts the interrupt from the int_n pin.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 39 of 142 jun 28,2013 ? brdy interrupt enabled register [brdyenb] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pipebrdye ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? - - - - - - - - - - bit name function software hardware remarks 15 - 10 un assigned. fix to "0" . 9 -0 pipebrdye i nterrupts for each pipe are e nabled specify whether it is possible to write "1" to the brdy bit while detecting the brdy bit of each pipe. 0: interrupt output disabled 1: interrupt output enabled r/w r remarks * the b it number correspo nds to the pipe number. 2.9.2 brdy interrupt enabled bit of each pipe (pipebrdye) when the controller detects the brdy interrupt for the pipe for which the software has written "1" in this bit, it set s "1" to the brdysts register pipebrdy bit and to the intsts0 register brdy bit, and asserts an interrupt from the int_n pin. when at least one bit from the brdysts register pipebrdy bit set s "1", if the software modifies the register interrupt enabled bit from "0" to "1", the controller asserts an interrupt from the int_n pin . ? nrdy interrupt enabled register [nrdyenb] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pipenrdye ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? - - - - - - - - - - bit name function software hardware remarks 15 - 10 un assigned. fix to "0" . 9 -0 pipenrdye nrdy interrupt for each pipe is enabled specify whether it is possible to write "1" to the nrdy bit while detecting the n rdy interrupt of each pipe. 0: interrupt output disabled 1: interrupt output enabled r/w r remarks * bit number cor responds to the pipe number. 2.9.3 nrdy interrupt enabled bit of each pipe (pipenrdye) when the controller detects the nrdy interrupt for the pipe for which the software has written "1" to this bit, it set s "1" to the nrdysts register pipebrdy bit and to the in tsts0 register nrdy bit, and asserts an interrupt from the int_n pin. when at least one bit from the nrdysts register pipenrdy bit set s "1", if the software modifies the interrupt enabled bit of the register from "0" to "1", the controller asserts an int errupt from the int_n pin .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 40 of 142 jun 28,2013 ? bemp interrupt enabled register [bempenb] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pipebempe ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? - - - - - - - - - - bit name function software hardware remarks 15 - 10 un assigned. fix to "0" . 9 -0 pipebempe bemp interrupt for each pipe is enabled specify whether it is possible to write "1" to the bemp bit while detecting the bemp interrupt of each pipe. 0: interrupt output disabled 1: interrupt output enabled r/w r remarks * bit number cor responds to the pipe number. 2.9.4 bemp interrupt enabled bit of each pipe (pipebempe) when the controller detects the bemp interrupt for the pipe for which the software has written "1" to this bit, it set s "1" to the pipebemp register pipebemp bit and to the i ntsts0 register bemp bit, and asserts an interrupt from the int_n pin. when at least one bit from the bempsts register pipebemp bit set s "1", if the software modifies the register interrupt enabled bit from "0" to "1", the controller asserts an interrupt from the int_n pin .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 41 of 142 jun 28,2013 2.10 sof c ontrol r egister ? sof pin configuration register [sofcfg] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 brdym intl edgests sofm ? ? ? ? ? ? ? ? ? 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? - - - - - ? ? bit name function software hardware remarks 15 - 7 un assi gned. fix to "0". 6 brdym pipebrdy interrupt status clear timing setting specify the timing for clearing the pipebrdy interrupt status. 0: software clears the status 1: hardware clears the status by read operation of the fifo buffer or by write operation to the fifo buffer t his bit can be set to o nly initializing . do not change the setting after operating. r/w r 5 intl i nterrupt output sense setting specify interrupt output sense of the int_n pin. 0: edge sense 1: level sense r/w r 4 edgests interrupt edge process status interrupt edge process status is set . 0: interrupt edge non - active 1: interrupt edge active r/w r 3 -2 sofm sof pin settings select sof pulse output mode. 00: sof output disabled 01: sof output in 1ms unit 10: sof output in 125s unit 11: reserved r/w r 1 - 0 un assigned. fix to "0". remarks * while writing "brdym=1", write "intl=1" ( l evel sense). * while writing "intl=0", clear interrupt status, confirm "edgests=0" to stop the system clock ( write "scke=0") and then write "scke=0".
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 42 of 142 jun 28,2013 2.11 i nterrupt s tatuses ? interrupt status register 0 [intsts0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vbint resm sofr dvst ctrt bemp nrdy brdy vbsts dvsq valid ctsq 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 - - - 1 - - - - - 0 0 1 - - - - bit name function software har dware remarks 15 vbint vbus change detect interrupt status vbus change detection interrupt status is set . 0: vbus interrupts not issued 1: vbus interrupts issued r/w(0) w 14 resm resume interrupt status resume detection interrupt status is set . 0: resum e interrupts not issued 1: resume interrupts issued r/w(0) w 13 sofr frame number update interrupt status frame number refresh interrupt status is set . 0: sof interrupts not issued 1: sof interrupts issued r/w(0) w 12 dvst device state transition inter rupt status device state transition interrupt status is set . status 0: device state transition interrupts not issued 1: device state transition interrupts issued r/w(0) w 11 ctrt control transfer stage transition interrupt s tatus control transfer stage t ransition interrupt s tatus is set . status 0: control transfer stage transition interrupts not issued 1: control transfer stage transition interrupts i ssued r/w(0) w 10 bemp bemp interrupt status bemp interrupt status is set . 0: bemp interrupts not issued 1: bemp interrupts issued r w 9 nrdy nrdy interrupt status nrdy interrupt status is set . 0: nrdy interrupts not issued 1: nrdy interrupts issued r w 8 brdy brdy interrupt status brdy interrupt status is set . 0: brdy interrupts not issued 1: brdy inter rupts issued r w 7 vbsts vbus input status input status of vbus pin is set . 0: vbus pin is "l" level 1: vbus pin is "h" level r w 6 -4 dvsq device state device state is set . 000: powered state 001: default state 010: address state 011: configured state 1xx: suspended state r w 3 valid usb request reception usb request reception detection valid/invalid is set . 0: not detected 1: setup packet reception r/w(0) w 2 -0 ctsq control transfer stage control transfer stage is set . 000: idle or setup stage 001: control read data stage 010: control read status stage 011: control write data stage 100: control write status stage 101: control write ( n o d ata) status stage 110: control transfer sequence error 111: reserved r w
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 43 of 142 jun 28,2013 remarks * to clear the status indicate d by the vbint , resm , sofr , dvst or c trt bit s , write "0" only for the bit to be cleared, and write "1" for other bits. do not write "0" to the status bit set to "0". * the controller detects the change in status indicated by the vbint and resm bits of this register , even while the clock is being stopped ("scke=0"), and notifies the interrupt if the corresponding interrupt is enabled. when the clock is enabled, cl ear the status using software. 2.11.1 vbus conversion interrupt status bit (vbint) when the controlle r detects the change in the vbus pin input value (from high to low and from low to high), "1" is written to this bit. the controller writes the input value of the vbus pin to the vbsts bit . when the vbint interrupt occurs , use the software to execute a con sistency check several times during the vbsts bit read , and reject the chattering. w hen detect to attach or detach ,please process as follows. (1)when detect to attach : s et drppu bit to ? 1 ?. (2)w hen detect to detach: p lease process as follows. (a ) s et drppu bit to ?0 ?. (b) wait for 1us (1000ns) (c) s et dcfm bit to ? 1 ? (b) wait for 200n s (e) s et dcfm bit to ?0 ? 2.11.2 resume interrupt status bit (resm) t he controller is in s uspend status (dvsq=1xx), and "1" is set to this bit when the dp pin fallin g edge is detected. 2.11.3 frame number update interrupt status bit (sofr) the conditions when the controller sets "1" in this bit are below. while updating the frame number, the controller sets "1" to this bit ( t his interrupt is detected every 1ms) . the contro ller detects the sofr interrupt by internal interpolation even if the sof packet from the usb host is corrupted . 2.11.4 device state transition interrupt status bit (dvst) i f the controller detects a change in the device state, it updates the dvsq value and set s "1" to this bit. when this interrupt occurs, clear the status before the controller detects the next device status state transition.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 44 of 142 jun 28,2013 2.11.5 control transfer and stage transition interrupt status bit (ctrt) i f the controller detects the stage transition of con trol transfer, it updates the ctsq value and set s "1" to this bit. when this interrupt occurs, clear the status before the controller detects stage transition after the control transfer. 2.11.6 buffer empty interrupt status bit (bemp) the controller set s "1? i n the interrupt when, among the bempsts register pipebemp bit s corresponding to the pipe for which "1" is written to the bempenb register pipebempe bit (when the controller detects the bemp interrupt status for at least one pipe from the pipe s for which th e software has enabled the bemp interrupt notification), at least one bit is "1". refer to the pipebemp register for assert conditions of the pipebemp status. if the software writes "0" for all the pipebemp bits corresponding to the pipe that is enable d by the pipebempe bit, the controller clears this bit to "0?. this bit cannot be cleared to "0" even if "0" is written to this bit by the software. 2.11.7 buffer not ready interrupt status bit (nrdy) the controller set s "1" in the interrupt when, among the nrdy sts register pipenrdy bits corresponding to the pipe for which "1" is written to the nrdyenb register pipenrdye bit (when the controller detects the nrdy interrupt status for at least one pipe from the pipes for which the software has enabled the nrdy inte rrupt notification), at least one bit is "1". refer to the pipenrdy register for assert conditions of the pipenrdy status. if the software writes "0" to all the pipenrdy bits corresponding to the pipe that is enabled by the pipenrdye bit , the controlle r clears this bit to "0". this bit cannot be cleared to "0? even if the software writes "0" to this bit. 2.11.8 buffer ready interrupt status bit (brdy) the controller set s "1" in the interrupt when, among the brdysts register pipebrdy bits corresponding to the pipe for which "1" is written in the brdyenb register pipebrdye bit (when the controller detects the brdy interrupt status for at least one pipe from the pipes for which the software has enabled the brdy interrupt notification), at least one bit is "1". refer to the pipebrdy register for the assert conditions of the pipebrdy status. if the software writes "0" to all the pipebrdy bits corresponding to the pipe that is enabled by the pipebrdye bit , the controller clears this bit to "0". this bit cannot be cleared to "0" even if the software writes "0" to this bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 45 of 142 jun 28,2013 ? brdy interrupt status register [brdysts] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pipebrdy ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? - - - - - - - - - - bit name function software hardware remarks 15 - 10 un assigned. fix to "0". 9 -0 pipebrdy brdy interrupt status of each pipe brdy interrupt status of each pipe is set . 0: i nterrupt not issued 1: i nterrupt issued r/w(0) w remarks * bit number corresponds to the pipe number. * if writing "brdym=0", to clear the status of each bit of this register, write "0" only to the bit that is to be cleared and "1" to other bits. * if writing "brdym=0", clear this interrupt before accessing the fifo. 2.11.9 brdy interrupt status bit of each pipe (pipebrdy) when the brdy interrupt is detected for the pipe with the controller, the controller s et s "1" in the brdysts register pipebrdy bit. here, by using the software when "1" is written to the bit corresponding to brdyenb register, the controller s et s "1" to the intsts0 register bdy bit and asserts the in terrupt from the int_n pin. for the brdy interrupt, occurrence conditions and clearing method change according to the brdym and bfre bits of each pipe. 2.11.9.1 writing "brdym=0 " and " bfre=0" for these, the brdy interrupt indicates the possibility of access to t he fifo port. in the following conditions, the controller issues the internal brdy interrupt request trigger and s et s "1" in the pipebrdy bit corresponding to the pipe for which a request trigger was issued. (1) when the pipe is set to transm it (a) when t he software has modified the dir bit from "0" to "1" . (b) when the controller ends the packet transmission of the pipe in the condition where write is not possible from the cpu to the fifo buffer that has been assigned to the pipe (when the bsts bit read v alue is "0") . when set to continuous t ransmission/ r eception, the request trigger is issued when transmission of one fifo buffer is complete. (c) when the fifo buffer is set to double buffer, one side of the fifo buffer is empty even if writ ing to other sid e is completed. during writ ing to the fifo buffer, the request trigger is not issued until write on other side is completed, even if write on one side is completed. (d) in an i sochronous transfer type pipe , when the hardware causes a buffer flash. (e) when the status of the fifo bit has been modified from " w rite disabled" to " w rite enabled" by writing "1" to the aclrm bit . request trigger is not issued for dcp ( i n other words, in data transmission of control transfer). (2) when the pipe is set to receive (a) when the controller ends the packet transmission of the pipe in the condition where write is not possible from the cpu to the fifo buffer that has been assigned to the pipe (when the bsts bit read value is "0") . a r equest trigger is not issued for the transaction of data pid mismatch. when set to continuous t ransmission/ r eception mode, the request trigger is issued when transmission of one fifo buffer is complete. when a short packet is received, the request trigger is issued even if space is available in the fifo buffer. while using the transaction counter, a request trigger is issued when a packet of setup value is received. here, the request trigger is issued even if space is available in the fifo buffer. (b) when the fifo buffer is set to double buff er, if the fifo buffer read is complete, o ne more fifo buffer read becomes possible . i f one more buffer is received during read, the request trigger is not issued until the read of the current buffer is completed.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 46 of 142 jun 28,2013 t his interrupt is not issued during commu nication with the control transfer status stage. the software can write to (clear) the pipebrdy interrupt status of the pipe to "0" by writing "0" to the bit corresponding to the pipe of this bit. here, write "0" to the bits corresponding to other pipe s. clear the interrupt status before accessing the fifo buffer. 2.11.9.2 writing "brdym=0 " and " bfre=1" if writing these, when the controller reads all the data of one transfer in reception pipe , it is determined that a brdy interrupt was issued and "1" is set in th e bit corresponding to the pipe of register. in either of the following conditions, it is determined that the controller receives the final data in one transfer : (1) when a short packet , including a zero - length packet , is received (2) when a packet of trnc nt bit s etup value is received by using transaction counter ( trncnt bit ) when this data is read after fulfilling the above - mentioned determination conditions, the controller concludes that the entire data of one transfer is read. if a zero - length packet is received when the fifo buffer is empty, the controller concludes that the entire data of one transfer is read when the frdy bit is "1" and the dtln bit is "0" ( there are in the fifo port control register ). in this case, to start the next transfer by usi ng the software, write "1" to the bclr bit of corresponding fifoctr register. if writing these, the controller does not detect brdy interrupt for the transmission pipe. the software can write to (clear) the pipebrdy interrupt status of the pipe to "0" by writing "0" to the bit corresponding to the pipe of this bit , and by writing "1" to the bit corresponding to other pipe. while using this mode, do not modify the s etup value of bfre bit until the transfer process is completed. while modifying bfre bi t during the process, clear all the fifo buffers of the corresponding pipe by aclrm bit. 2.11.9.3 writing "brdym=1 " and " bfre=0" if writing these, the bit value is coupled with the pipe ? s bsts bit. in other words, the controller s et s "1" or "0" depending on the fi fo buffer status of brdy interrupt status. (1) when the pipe is set to transmi t. set s "1" when the data can be written in the fifo port, otherwise set s "0". however, the brdy interrupt is not asserted even if the dcp transmission pipe can be written to . (2 ) when the pipe is set to rece ive. set s "1" when the data can be written in the fifo port, and "0" when all the data is read (status changed to "read disabled" status). when the fifo buffer is empty and a zero - length packet is received, "1" is set in the corresponding bit until the software writes "bclr=1", and the brdy interrupt is asserted." if writing these, the software cannot write "0" to th is bit. i f writing "brdym=1", write "0" to all the bfre bits (all pipe s ). if writing "brdym=1", write "1" to the intl bit ( l evel control).
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 47 of 142 jun 28,2013 ? nrdy interrupt status register [nrdysts] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pipenrdy ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? - - - - - - - - - - bit name function software hardware remark s 15 - 10 un assigned. fix to "0". 9 -0 pipenrdy nrdy interrupt status of each pipe nrdy interrupt status of each pipe is set . 0: i nterrupt not issued 1: i nterrupt issued r/w(0) w(1) remarks * bit number corresponds to the pipe number. * to clear the stat us indicated by each bit of the register, write "0"only the bit to be cleared and other bits to "1". 2.11.10 nrdy interrupt status bit of each pipe (pipenrdy) for the pipe set to "pid=buf" by the software, when the internal nrdy interrupt request is issued by the controller , it set s "1" to the bit corresponding to the nrdysts register pipenrdy bit. here, when the software is used to write "1" to the bit corresponding to the nrdyenb register, the controller set s "1" in the intsts0 register nrdy bit and asserts the interrupt from the int_n pin. th e c onditions that this controller generates the nrdy interrupt request for the pipe is shown below . but a n interrupt request is not issued while executing the control transfer status stage. 2.11.10.1 (1) when the pipe is transmitting: (a) when an in token is received while there is no transmission data in the fifo buffer and the corresponding pipe pid bit is set to ? buf ? (?01 ?): while receiving the i n - token, the controller issues an nrdy interrupt and set s "1" to the pipenrdy bit. if the in terrupt pipe transfer type is isochronous, the controller sends a zero - length packet and set s "1" to the ovrn bit. (2) when the pipe is receiving: (a) when the corresponding pipe pid bit is set to ? buf ? (?01 ? ) and an out token is received while there is no open space in the fifo buffer: if an interrupt pipe transfer type is isochronous, when the o ut - token is received, the controller issues a nrdy interrupt, set s "1" to the pipenrdy bit and set s "1" to the ovrn bit . if the interrupt pipe transfer type is not isoch ronous, the controller issues a nrdy interrupt request while sending a nak h andshake after receiving the data in continuation with an o ut - token, and set s "1" to the pipenrdy bit. however, while resending (when data - pid mismatch occurs), a nrdy interrupt re quest is not issued. if there is a data packet error, the request is not issued. (b) when the corresponding pipe pid bit is set to ? buf ? (?01 ? ) and a ping token is received while there is no open space in the fifo buffer: while receiving the ping - token, the controller issues nrdy interrupt and set s "1" to the pipenrdy bit . (c) in an isochronous transfer pipe, when the pid bit is set to ? buf ? (?01? ) and data is not received successfully within the interval frame: the controller issues nrdy interrupt request and set s "1" to the pipenrdy bit in the sof reception timing.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 48 of 142 jun 28,2013 ? bemp interrupt status register [bempsts] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pipebemp ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? - - - - - - - - - - bit name functi on software hardware remarks 15 - 10 un assigned. fix to "0". 9 -0 pipenrdy bemp interrupt status of each pipe bemp interrupt status of each pipe is set . 0:interrupt not issued 1:interrupt issued r/w(0) w(1) remarks * bit number corresponds to the pipe nu mber. to clear the status shown by each bit of this register, write "0" only for the bit to be cleared and "1" for the other bits. 2.11.11 bemp interrupt status bit of each pipe (pipebemp) for the pipe set as "pid=buf" by the software, when the controller uses th e software to detect the bemp interrupt , it set s "1" to the bit corresponding to the bempenb register. in this case, when using the software to write "1" to the bit corresponding to the bempenb register, the controller set s "1" to the intsts0 register bemp bit and asserts the interrupt from the int_n pin. the controller issues an internal bemp interrupt request in the following cases : (1) in the transmission pipe, when the fifo buffer of the corresponding pipe is empty on completion of transmission (includ ing transmission of the zero - length packet). when it is a single buffer setting, for the pipe other than the dcp, the internal bemp interrupt request is issued simultaneously with the brdy interrupt. however, the internal bemp interrupt request is not is sued in the following cases : (a) i f writing to a double buffer, when the software (dmac) starts the data write for the fifo buffer on the cpu side after completion of data transmission on one side. (b) buffer clear by writing "1" to the aclrm bit or bclr b it ( e mpty). (c) in transfer of control transfer s tatus stage (zero - length packet transmission) (2) in the rece iving pipe when the data size greater than the s etup value of the maximum packet size is received normally . i n this case, the controller issues t he bemp interrupt request , set s "1" in the bit corresponding to the pipebemp bit, deletes the reception data . t he pid bit is changed to "stall"("11")" , and stall respon ds . however, the internal bemp interrupt request is not issued in the following cases : (a) when a crc error or bit stuffing error, etc. , have been detected in the reception data (b) while executing a s etup transaction the status can be cleared by writing "0" to this bit. no process is executed even if "1" is written to this bit .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 49 of 142 jun 28,2013 2.12 frame numb er register ? frame number register [frmnum] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ovrn crce frnm 0 0 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 - - ? ? ? - - - - - - - - - - - bit name function software hardware remarks 15 ovrn overrun/underrun detect statu s whether overrun/underrun error is detected or not is set for the pipe transferred isochronously. 0: no error 1: error r/w(0) w 14 crce crc error detect status whether crc error is detected or not is set for the pipe transferred isochronously. 0: no err or 1: error r/w(0) w 13 - 11 un assigned. fix to "0". 10-0 frnm frame number latest frame number is displayed. r w remarks * the ovrn bit is used for debugging. set the timing so that an overrun/underrun error does not occur in the system. 2.12.1 overrun/unde rrun detection status bit (ovrn) in an i sochronous transfer type pipe , the controller set s "1" to this bit when an o verrun/ u nderrun is detected. when an o verrun/ u nderrun is detected, the controller issues an internal nrdy request. refer to 2.11.10 for details. the software can clear this bit to "0" by writing "0" to this bit. in this case, write " 0x4000 " to this register when do not clear crce at the same time . the controller set s "1" to this bit in either of the following cases : (1) when data has not been written completely to the fifo buffer despite transmission, and the in - token is received in the i sochronous transfer type transmission pipe . (2) when at least one part of the fifo buffer is not free, and the o ut - token is received in the i sochronous transfer rece iving pipe . 2.12.2 crc error detection status bit (crce) in an i sochronous transfer pipe , the controller set s "1" to the bit when a crc error or bit stuffing error has been detected. the software can clear this bit to "0" by writing "0" to this bit. in this case, write " 0x8000 ? to this register when do not clear ovrn at the same time . when a crc error or bit stuffing error is detected, the controller issues an internal nrdy request. refer to 2.11.10 for details. 2.12.3 frame number bit (frnm ) the controller updates the sof issue timing every 1ms or updates this bit during sof reception, and set s the frame number. check the consistency twice during read of this bit by t he software.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 50 of 142 jun 28,2013 ? frame number register [ufrmnum] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ufrnm ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? - - - bit name function software hardware remarks 15 - 3 un assigned. fi x to "0". 2 -0 ufrnm microframe microframe number is set . r w remarks none 2.12.4 microframe number bit (ufrmnum) for the hi - speed, the controller displays the microframe number in this bit. in case of hi - speed, the controller sets 0x00 to this bit. use sof tware to c heck the consistency twice when this bit is being read .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 51 of 142 jun 28,2013 2.13 usb a ddress ? usbaddress register [usbaddr] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usbaddr ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 bit name function software hardware remarks 15 - 7 un assigned. fix to "0". 6 -0 usbad dr usbaddress usb a ddress confirmation assigned from the host is set . r r/w remarks 2.13.1 usb a ddress bit (usbaddr) t he usb a ddress received in this bit is set when the s et a ddress request is processed normally by the controller. i f a usb bus reset is detect ed by the controller, 0x00 is set to this bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 52 of 142 jun 28,2013 2.14 usb request register the usb request register is the register for saving the control transfer setup request. t he received usb request value is stored. ? usb request type register [usbreq] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 brequest bmrequesttype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name function software hardware remarks 15-8 brequest request usb re quest brequest value r w 7 -0 bmrequest t ype request type usb request bmrequest t ype value r w remarks none 2.14.1 usb request bit (brequest) the usb request data value received in the setup transaction by the controller is displayed in this bit. it is not po ssible (i nvalid) to write to this bit using the software . 2.14.2 usb request bit (brmrequesttype) the usb request data value received in the setup transaction by the controller is set to this bit. it is not possible (i nvalid) to write to this bit using the softw are . ? usb request value register [usbval] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wvalue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name function software hardware remarks 15-0 wvalue value usb request wval ue value r w remarks none 2.14.3 value bit (wvalue) this is the bit to write and read the value of the usb request wvalue. b7- 0 is a lower byte. the usb request wvalue value received in the setup transaction by the controller is set in this bit. it is not po ssible (i nvalid) to write to this bit using the software .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 53 of 142 jun 28,2013 ? usb request index register [usbindx] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 windex 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name function software hardware remarks 15-0 windex index usb request windex value r w remarks none 2.14.4 index bit (windex) this is the bit to write and read the value of the usb request windex. b7- 0 is a lower byte. the usb request windex value received in the setup transaction by the controller is set in this bit. it is not possible (i nvalid) to write to this bit using the software . ? usb request index register [usbleng] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wlength 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name function software hardware remarks 15-0 wlength length usb request wlength value r w remarks none 2.14.5 length bit (wlength) this is the bit to write and read the value of the usb request wlength. b7- 0 is a lower byte. the usb request wlength value received in setup transaction by the controller is set in this bit. it is not possi ble to write to this bit using the software .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 54 of 142 jun 28,2013 2.15 dcp configuration when using the control transfer for data communication, use the default control pipe (dcp). ? dcp configuration register [dcpcfg] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cntmd shtnak ? ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? - - ? ? ? ? ? ? ? bit name function software hardware remarks 15 - 5 un assigned. fix to "0". 8 cntmd continuous transfer mode specifies whether to connect the pipe in continuous transfer mode. 0: non - continuous transfer mode 1: continuous transfer mode r/w r 7 shtnak pipe disabled at the end of transfer for pipe reception direction, speci fies whether to modify pid to nak during transfer end. 0: pipe continued at end of transfer 1: pipe disabled at end of transfer r/w r 6 - 0 un assigned. fix to "0". remarks the cntmd bit becomes a common bit in either direction of forwarding so that the b uffer memory of dcp may use the common buffer by the control lead forwarding and the control light forwarding. ? dcp maximum packet size register [dcpmaxp] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mxps ? ? ? ? ? ? ? ? ? 1 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? - - - - - - - bit name function software hardware remarks 1 5 - 7 un assigned. fix to "0". 6 -0 mxps maximum packet size this specifies the maximum payload (maximum packet size) for the dcp. r/w r remarks none 2.15.1 maximum packet size bit (mxps) write the maximum data payload of the dcp (maximum packet size) to this bit. 0x40 (64 b ytes) is the default value. set the values according to the usb specification revision 2.0 while writing the mxps bit. not write to the mxps bit except when "pid=nak" , and when the pipe in the curpipe bit is not written . to modify this bit after changing the pid bit of the corresponding pipe from "buf" to "nak", check that "pbusy=0", and then modify th e bit. however, when the controller modifies the pid bit t o "nak", it is not necessary to check the pbusy bit. when "mxps=0" is written , do not write to the fifo buffer or write "pid=buf".
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 55 of 142 jun 28,2013 ? dcp control register [dcpctr] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bsts sqclr sqset sqmon pbusy ccpl pid 0 ? ? ? ? ? ? 0 0 1 0 ? ? 0 0 0 - ? ? ? ? ? ? - - - - ? ? 0 0 0 bit name function software hardware remarks 15 bsts bu ffer status access possibility status of dcp fifo buffer is set . 0: buffer access is disabled 1: buffer access is enabled r w 1 4 - 9 un assigned. fix to "0". 8 sqclr toggle bit clear in dcp transfer, the expected value of sequence toggle bit of next transa ction can be written to data0. 0: invalid 1: specifies data0 r(0)/w(1) r 7 sqset toggle bit set in the dcp transfer, the expected value of the sequence toggle bit of the next transaction can be written to data1. 0: invalid 1: specifies data1 r(0)/w(1) r 6 sqmon sequence toggle bit monitor in the dcp transfer, the expected value of the sequence toggle bit of the next transaction is set . 0: data0 1: data1 r w 5 pbusy p ipe busy sets whether the pipe is being used by the current usb bus. 0: p ipe not used in the usb bus 1: p ipe used in the usb bus r w 4 - 3 un assigned. fix to "0". 2 ccpl control transfer end enabled s tatus stage end of control transfer is enabled by writing "1" to this bit . 0: invalid 1: control transfer end enabled r(0)/w(1) r/w(0) 1 -0 pid response pid this bit c ontrols the controller response in the control transfer. 00: nak response 01: buf response ( conforms with the buffer state) 10: stall response 11: stall response r/w r/w remarks none 2.15.2 buffer status bit (bsts) the controller i ndicates by this bit whether access of the fifo buffer assigned to the dcp is possible from the cpu. the meaning of this bit differs according to the s etup value of the isel bit as follows : (1) when "isel=0": indicates whether read of reception data is pos sible. (2) when "isel=1": indicates whether write of transmission data is possible. 2.15.3 clear bit of sequence toggle bit (sqclr) if the software writes "1" to this bit, the controller writes the expected value of the sequence toggle bit of the pipe to data0. the controller always set s "0" to this bit. do not write "1" to the sqclr bit and sqset bit simultaneously. write "1" to this bit when "pid=nak". to write "1" to this bit after modify ing the pid bit of the corresponding pipe from "buf" to "nak", check t hat "pbusy=0", and then write th e bit. however, since the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 56 of 142 jun 28,2013 2.15.4 sequence toggle bit s et bit (sqset) if the software writes "1" to this bit , the controller writes the expec ted value sequence toggle bit of the pipe to data1. the controller always set s "0" to this bit. do not write "1" to the sqclr bit and sqset bit simultaneously. write "1" to this bit when "pid=nak". to write "1" to this bit after modifying the pid bit o f the corresponding pipe from "buf" to "nak", check that "pbusy=0" , and then write th e bit. however, since the controller modifies the pid bit to "nak", it is not necessary to check the pbusy bit . 2.15.5 sequence toggle bit m onitor bit (sqmon) the controller set s the expected value of the sequence toggle bit of the pipe in this bit. if a normal process is executed for the transaction, the controller toggles this bit. however, the bit is not toggled when a data - pid mismatch occurs during reception transfer. t h e controller writes "1" to this bit ( write s the expected value to "1") when the setup packet is received normally. t he controller does not refer to this bit during in/out transaction of the status stage. it does not toggle the bit even if the process is c ompleted normally. 2.15.6 p ipe busy bit (pbusy) the controller modifies this bit from "0" to "1" when the usb transaction of the pipe is started. this bit is modified from "1" to "0? when one transaction is complete. when the software has written "pid=nak", it is possible to check whether the pipe setting can be modified by read ing this bit. 2.15.7 control transfer end enabled (ccp l ) i f the corresponding pid bit is "buf" and the software writes "1" to this bit, the controller completes the control transfer stage. in other words, it transmits an ack h andshake for the out transaction from the usb h ost during a control read transfer, and transmits a zero - length packet for an in transaction from the usb h ost during a control write and no data control transfer. however, ir respective of the s etup value of this bit, the controller responds automatically from the setup stage until the status stage is complete when a set_address request is detect ed. when a new setup packet is received, the controller modifies this bit from "1 " to "0". when " valid =1", the software cannot write "1" to this bit. 2.15.8 response pid bit (pid) for this bit, while executing data stage or status stage of control transfer, use the software to modify this bit from "nak" to "buf". the controller modifies the bit value in the following cases : (1) when the controller receives the setup packet, the controller modifies this bit to "nak" ("00"). here, the controller set s "valid=1 " and the software cannot modify this bit until it writes "valid=0". (2) when the s oftware writes "buf" to this bit and the controller receives the data exceeding the maximum packet size , the controller set s "pid=stall(11)". (3) when the controller detects a control transfer sequence error, it set s "pid=stall(1x)". (4) when the controlle r detects a usb bus reset, it set s "pid=nak". during a set_address request process (auto process), the controller does not refer to the s etup value of this bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 57 of 142 jun 28,2013 2.16 p ipe configuration register p ipe1 - pipe 9 should be written to using the pipesel , pipecfg , pi pebuf , pipemaxp , pipeperi , pipexctr , pipextre and pipextrn registers. after selecting the pipe using the pipesel register, write to the pipe functions using the pipecfg , pipebuf , pipemaxp and pipeperi registers. the pipexctr , pipextre and pipextrn register s can be written to separately from the pipe selection specified with the pipesel register, with no relation between them. ? pipe window selection register [pipesel] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pipesel ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? - - - - bit name function software hardware remarks 15 - 4 un assigned. fix to "0". 3 -0 pipesel pipe window selection specifies pipe related to address68h - 6eh register. 0000: not selected 0001: pipe1 0010: pipe 2 0011: pipe3 0100: pipe4 0101: pipe5 0110: pipe6 0111: pipe7 1000: pipe8 1001: pipe9 r/w r remarks * when "pipesel=0000", "0" is read from all of the bits of the related registers noted above. when "pipesel=0000", write to the pipe related to address68 h - 6eh register is invalid. 2.16.1 pipe window selection bit (pipesel) if the software writes "0001" to "1001" to this bit , the controller displays the pipe information and the s etup value corresponding to the registers from a ddress h68 to h6c. after pipe specifi cation writing of this bit, the value written by the software in a ddress h68 to h6c is reflected in the corresponding pipe transfer method. if the software writes "0000" to this bit , the controller sets s all "0" in the register from a ddress h68 to h6c. us ing software to w rit e to a ddress h68 to h6c is invalid.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 58 of 142 jun 28,2013 ? pipe configuration register [pipecfg] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 type bfre dblb cntmd shtnak dir epnum 0 0 ? ? ? 0 0 0 0 ? ? 0 0 0 0 0 - - ? ? ? - - - - ? ? - - - - - bit name function software hardware remarks 15-14 type transfer type specifies transfer type of pipe specified in pipesel bit. 00: pipe use disabled 01: bulk transfer 10: interrupt transfer 11: isochronous transfer r/w r 13 - 11 un assigned. fix to "0". 10 bfre brdy interrupt operation specified specifies the notification timing related to the pipe from the controller. 0: brdy interrupt notification upon sending or receiving data 1: brdy interrupt notification upon reading data r/w r 9 dblb doubl e buffer mode specifies whether the fifo buffer used by the pipe is single buffer or double buffer. 0: single buffer 1: double buffer r/w r 8 cntmd continuous transfer mode specifies whether to connect the pipe in continuous transfer mode. 0: non - continu ous transfer mode 1: continuous transfer mode r/w r 7 shtnak pipe disabled at the end of transfer for pipe reception direction, specifies whether to modify pid to nak during transfer end. 0: pipe continued at end of transfer 1: pipe disabled at end of tr ansfer r/w r 6 - 5 un assigned. fix to "0". 4 dir transfer direction specifies pipe transfer direction. 0: rece ive 1: transmi t r/w r 3 -0 epnum endpoint number specifies endpoint number of pipe. r/w r remarks none
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 59 of 142 jun 28,2013 2.16.2 transfer type bit (type) for this bit , write to usb transfer type of pipe ( s elected pipe) written to the pipesel bit. a list of transfer types that can be written to the selected pipe and this bit are shown in table 2.11 . table 2 . 11 list of t ransfer t ypes t hat c an b e written to t he s elected p ipe & type bit s e le c ted p ipe type b it usb t ransfer t ype pipe1 or pipe2 "01" or "11" bulk or isochronous transfer pipe3 ~ pipe5 "01" bulk transfer pipe6 ~ pipe9 "10 " interrupt transfer write a value other than "00" to this bit and then write "pid=buf" (usb communication is started by writing "pid=buf" when using the selected pipe). this bit can be modified when the pid bit of the selected pipe is in "nak" status. to modify this bit after chenging the pid bit of the selected pipe from "buf" to "nak", check that "pbusy=0" , and then modify th e bit. however, when the controller modifies the pid bit to "nak", it is not necessary to check the pbusy bit. 2.16.3 brdy interrupt operation specification bit (bfre) this bit is valid when the selected pipes are pipe1 to pipe5. when the software has written "1" to this bit and the selected pipe is used in reception, (i.e. when "dir bit=0" is written ), the controller detects transfer completion and issues a brdy interrupt when that packet is completely read. when the brdy interrupt is issued with these settings, the software need write "bclr=1". the status of the fifo buffer assigned to the selected pipe does not change to rece ive sta tus until "bclr=1". the software writes "1" to this bit and the selected pipe is used in transmission , (i n other words when "dir bit=1" is written ) the controller does not issue the brdy interrupt. refer to the pipebrdy interrupt register for details. t his bit can be modified when "pid=nak" , and when the pipe is in the curpipe bit is not written . execute usb communication by using the selected pipe, use the software to continuously write "aclrm=1" and "aclrm=0", clear the fifo buffer assigned to the sele cted pipe, and then modify this bit in addition to the status of the above three registers. to modify this bit after chenging the pid bit of the selected pipe from "buf" to "nak" , c heck that "pbusy=0", and modify th e bit. however, when the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 60 of 142 jun 28,2013 2.16.4 double buffer mode bit (dblb) this bit is valid when the selected pipe is pipe1 to pipe5. when the software writes "1" to this bit, for the selected pipe the controller assign s the fifo buffer size equal to two sides specified by the pipebuf register bufsize bit . in other words, the size of the fifo buffer that is assigned by the controller to the selected pipe is given below. (bufsize+1)*64*(dblb+1) [byte] when the software writes "1" to this bit, and the selected pipe is used in transmission ( written to "dir bit=1"), the controller does not issue a brdy interrupt. refer to the pipebrdy interrupt register for details. this bit can be modified when "pid=nak" , and when the pi pe in the curpipe bit is not written . execute usb communication using the selected pipe, use the software to continuously write "aclrm=1" and "aclrm=0", clear the fifo buffer assigned to the selected pipe, and then modify this bit in addition to the status of the above three registers. check that "pbusy=0", modify the pid bit of the selected pipe from "buf" to "nak" and then modify this bit. however, when the controller has modified the pid bit to "nak", it is not necessary to use the software to check th e pbusy bit. 2.16.5 continuous transfer mode bit (cntmd) this bit is valid when p ipe 1 to p ipe 5 are selected and the transfer type of the selected pipe is set to b ulk. according to the s etup value of this bit , this controller determines t ransmission/ r eception completion for the fifo buffer assigned to the selected pipe, as shown in table 2.12 . table 2 . 12 relation b etween transmission/reception c ompletion d etermination for the cntmd setup v alue and the fifo b uffer cntmd bit setup value method of judging state that can be read or transmitted 0 if the reception direction has been written ("dir=0"), the condition when the status of the fifo buffer changes to read possible . w hen the controller has received one packet . if transmission direction has been written ("dir=1"), the condition when the status of the fifo buffer changes to transmission possible . when following conditions are fulfilled : (1) the software (or dmac) has written the data of maximum packet size in the fifo buffer. (2) the software (or dmac) has written the data of short packet (including the case of 0 byte) and "bval=1". 1 if the reception direction has been written ("dir=0"), the conditions when the statu s of the fifo buffer change to read possible when (1) , (2) , (3) or ( 4 ) from the following conditions is fulfilled : (1) when the number of bytes of received data in the specified fifo buffer of the selected pipe matches the set number of bytes ((bufsize+ 1)*64) (2) when the controller receives a short packet other than a zero - length packet (3) when the contoller receives a zero - length packet even though data is already stored in the specified fifo buffer of the selected pipe. (4) when the controller receiv es packet s as many as the transaction counter set for the selected pipe. if the transmission direction has been written ("dir=1"), the condition when the status of the fifo buffer changes to transmission possible . when (1) , (2) or ( 3 ) from the following conditions is fulfilled : (1) when the data count written by the software (or dmac) does match with one side of fifo buffer size assigned to the selected pipe. (2) when the software (or dmac) writes the data (including 0 byte s ) smaller than the data on one side of fifo buffer assigned to the selected pipe and "bval=1". (3) when the software writes the data (including 0 byte s ) smaller than the data on one side of fifo buffer assigned to the selected pipe and asserts the dendx_n signal simultaneously with writ e of the data for the
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 61 of 142 jun 28,2013 last time. this bit can be modified when "pid=nak" , and when the pipe in the curpipe bit is not written to . execute usb communication using the selected pipe, use the software to continuously write "aclrm=1" and "aclrm=0", clear the fifo buffer assigned to the selected pipe, and then modify this bit in addition to the status of the above three registers. to modify this bit after changing the pid bit of the corresponding pipe from "buf" to "nak", c heck that "pbusy=0", and modify th e bit. however, when the controller has modified the pid bit to "nak", it is not necessary tto check the pbusy bit. 2.16.6 p ipe disabled at the end of transfer bit (shtnak) this bit is valid when pipe1 to pipe 5 are selected and is rece iving . when the software ha s set "1" to this bit for the rece iving pipe, when the transfer end is determined for the selected pipe, the controller modifies the pid bit of the selected pipe to "nak". the controller determines transfer end when either one of the following conditions a re fulfilled : (1) when a short packet data (including a zero - length packet) is received normally. (2) when a transaction counter is used and a packet of transaction counter portion is received normally. this bit can be modified when "pid=nak". to modify this bit after changing the pid bit of the corresponding pipe from "buf" to "nak", c heck that "pbusy=0", and modify th e bit. however, when the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit. write "0" to this bi t for the transmission direction pipe ". 2.16.7 transfer direction bit (dir) when the software has written "0" to this bit and the controller has set the selected pipe to rece ive and "1" is written to this bit, the controller uses the selected pipe in transmissio n. this bit can be modified when "pid=nak" , and when the pipe in the curpipe bit is not written . execute usb communication using the selected pipe, use the software to continuously write "aclrm=1" and "aclrm=0", clear the fifo buffer assigned to the sele cted pipe, and then modify this bit in addition to the status of the above three registers. to modify this bit after changing the pid bit of the corresponding pipe from "buf" to "nak", c heck that "pbusy=0", and modify th e bit. however, when the controlle r has modified the pid bit to "nak", it is not necessary to check the pbusy bit. 2.16.8 endpoint number bit (epnum) in this bit, use the software to write the endpoint number related to the selected pipe. however, writing "0000" indicate s that the pipe is not be ing used. this bit can be modified when "pid=nak" , and when the in the curpipe bit is not written. to modify this bit after changing the pid bit of the corresponding pipe from "buf" to "nak", c heck that "pbusy=0", and modify th e bit. however, when the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit. set the combination of the dir bit and epnum bit so that they are not duplicated with the other pipe settings ("epnum=000" ( s elected pipe not used) settings can be duplicated) .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 62 of 142 jun 28,2013 ? pipe buffer specification register [pipebuf] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bufsize bufnmb ? 0 0 0 0 0 ? ? 0 0 0 0 0 0 0 0 ? - - - - - ? ? - - - - - - - - bit name function software hardware remarks 15 un assigned. fix to "0". 14-10 bufsize b uffer size specifies the fifo buffer size of pipe specified in pipesel bit. 0x00: 64 byte s 0x01: 128 byte s ... 0x1f: 2kbyte s ) r/w r 9 - 8 un assigned. fix to "0". 7 -0 bufnmb buffer number specifies the pipe fifo buffer number . (0x4 - 0 x87) r/w r remarks * not m odify each bit in the register except when the status of the software is "pid=nak" and the pipe is not set in the curpipe bit. * to modify each bit in the register after changing the pid bit of the selected pipe from "buf" to " nak" c heck that "pbusy=0" , and modify th e bit. however, when the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit. 2.16.9 buffer size bit (bufsize) in this bit, write to the fifo buffer size to be assigned to the pipe. it is measured in blocks, and one block is 64 b ytes. when the software has written "dblb=1", the controller assigns two sides of the fifo buffer specified by this bit for the selected pipe. the size of the fifo buffer that is assigned by the controller to the selected pipe is given below : (bufsize+1)*64*(dblb+1) [byte] for this bit, set the values in the following range : (1) when pipe1 to pipe5 are selected , the v alue from 0x0 to 0x1f can be written . (2) when pipe6 to pipe9 are selected , only 0x0 can be writt en . if writing "cntmd=1", write the value of the integral multiple of the maximum packet size in the bufsize bit. 2.16.10 buffer number bit (bufnmb) specify the first block number from the fifo buffer to be assigned to the pipe. the block of the fifo buffer ass igned for the selected pipe by the controller is given below : block number: bufnmb~block number: bufnmb+(bufsize+1)*(dblb+1) -1 for this bit, write the values within the range from 0 (0x00) to 8640 (0x87). however, observe the following conditions : 0x00 -0 x03 are exclusive to dcp. 0x04 is the dedicated pipe6. however, when pipe6 is not used, it can be used by other pipes . when the selected pipe is pipe6, write to this bit is disabled. the controller automatically assigns "bufnmb=0x04" to pipe6. 0x05 is the dedicated pipe7. however, when pipe7 is not used, it can be used by other pipes. when the selected pipe is pipe7, write to this bit is disabled. the controller automatically assigns "bufnmb=0x05" to pipe7. 0x06 is the dedicated pipe8. however, when pipe8 i s not used, it can be used by other pipes. when the selected pipe is pipe8, write to this bit is disabled. the controller automatically assigns "bufnmb=0x06" to pipe8. 0x07 is the dedicated pipe9. however, when pipe9 is not used, it can be used by other pi pes. when the selected pipe is pipe9, write to this bit is disabled. the controller automatically assigns "bufnmb=0x07" to pipe9.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 63 of 142 jun 28,2013 ? pipe maximum packet size register [pipemaxp] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mxps ? ? ? ? ? 0 0 0 0 0(1) 0 0 0 0 0 0 ? ? ? ? ? - - - - - - - - - - - bit name function software hardware remarks 15 - 11 un assigned. fix to "0". 10-0 mxps maximum packet size specifies maximum data payload ( m aximum packet size) of the pipe. pipe6 ? pipe 9 can be writt en from 0x1 to 0x40 bytes. r/w r remarks * the default value of the mxps bit is "0x00" when the pipesel register pipesel pipe is not selected, and "0x40" when selected. 2.16.11 maximum packet size bit (mxps) in this bit , write the maximum data payload (maximum packet size) of the selected pipe. for pipe1 and pipe 2, the value from 1 byte (0x1) to 1024 bytes (0x400) can be written . for pipe3 to pipe 5, values of 8 byte s (0x8), 16 byte s (0x10), 32 byte s (0x20), 64 byte s (0x40) and 512 byte s (0x200) can be written ( the [2:0] bit does not exist) . for p ipe 6 to pipe 9, value s from 1 byte (0x1) to 64 byte s (0x40) can be written . the d efault value is 0x40 (64 byte s ). in the mxps bit , write the values based on the usb specification revision 2.0 for each transfer type. w hile transmitting i sochronous pipe in split - transaction, write the value to less than 188 bytes in the mxps bit. not write the mxps bit except when "pid=nak" and values are not set in the curpipe bit. to modify this bit after chenging the pid bit of the pi pe from "buf" to "nak", check that "pbusy=0", and modify th e bit. however, when the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit. w hen "mxps=0" , d o not write anything in the fifo buffer and do not write "pid=bu f".
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 64 of 142 jun 28,2013 ? pipe timing control register [pipeperi] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ifis iitv ? ? ? 0 ? ? ? ? ? ? ? ? ? 0 0 0 ? ? ? - ? ? ? ? ? ? ? ? ? - - - bit name function software hardware remarks 15 - 13 un assigned. fix to "0". 12 ifis isochronous in buffer flush specifies buffer flushed/not - flushed when the transfer type of pipe specified in pipesel bit is i sochronous in . 0: the buffer is not flushed 1: the buffer is flushed r/w r 11 - 3 un assigned. fix to "0". 2 -0 iitv interval error detection spacing specifies the transfer interval timing of pipe as second power frame timing. r/w r remarks none 2.16.12 isochronous in buffer flush bit (ifis) this is the function in which the controller automatically clears the fifo bu ffer, if transfer type isochronous pipe, transfer is in transfer , and when the controller has not received the i n - token from the usb host in the (micro) frame for each i nterval specified in iitv bit. in the double buffer setting ( write "dblb=1"), the contr oller clears only the data on one side of the previous buffer. the fifo buffer is cleared when the sof packet is received immediately after the (micro) frame receives the i n - token. it is cleared also when the sof packet is corrup ed when the sof is to be re ceived by an internal interpolation function. if the selected pipe of other than transfer type isochronous, write "0" to this bit . 2.16.13 interval error detection spacing bit (iitv) in this bit, specify the interval error detection spacing to frame timing squ ared . not write to this bit except when "pid=nak" , and when the pipe in the curpipe bit is not written. to modify this bit after chenging the pid bit of the pipe from "buf" to "nak", check that "pbusy=0", and then modify th e bit. however, when the contro ller has modified the pid bit to "nak", it is not necessary to check the pbusy bit. wh en modifying the bit value, after execute usb communication, write "aclrm=1" after writing "pid=nak", and initialize the interval timer. this bit does not exist in pi pe3 to pipe 5. set "0" in the position of the bit corresponding to pipe3 to pipe 5. 2.16.13.1 if the selected pipe transfer type is isochronous, this bit can be written to . (1) if the selected pipe is an isochronous - out transfer pipe when the data packet is received in the (micro) frame for each interval set in iitv bit, the controller issues a nrdy interrupt. a nrdy interrupt is also issued when the data packet is not received due to error s such as a crc error or (due to reasons like the reading of data from fifo bu ffer by the software (dmac) is slow) when the controller cannot receive the data because the fifo buffer is full. a nrdy interrupt is issued when the sof packet is received. also , when the sof packet is corrupted, the interrupt is issued when the sof pac ket is to be received by an internal interpolation function. however, if other than "iitv=0", a nrdy interrupt is to be issued when the sof packet is received for each interval after starting interval counting. after activating the interval timer, when t he pid bit is written to "nak" by the software, the controller does not
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 65 of 142 jun 28,2013 (micro) frame s o f s o f s o f o u t d a t a 0 s o f s o f o u t d a t a 0 s o f s o f o u t d a t a 0 pid bit setup value n a k b u f b u f b u f b u f b u f b u f token reception expectation flag (0: reception expected - : not received is expected) - - 0 - 0 - 0 interval counting start ( micro ) frame s o f s o f s o f o u t d a t a 0 s o f o u t d a t a 0 pid bit setup value n a k b u f b u f b u f token reception expectation flag (0: reception expected - : not received is expected ) - - 0 0 interval counting start ? issue the nrdy interrupt even if the sof packet is received. the count start conditions of the interval differ according to the s etup value of the iitv bit (a) if "iitv=0": counting of the interval is started from the next (micro) frame after modifying the pid bit of the selected pipe to "buf" . figure 2 . 1 correlation between (micro) frame and token reception expectation flag when "iitv =0" (b) if other than "iitv=0": counting of interval is started when the initial data packet is received normally after modifying the pid bit of the selected pipe to "buf". figure 2 . 2 correlation between (m icro) frame and token reception expectation flag when "iitv= 1 " (2) when the selected pipe is an i sochronous in transfer pipe i t is used in combination with "ifis="1". if "ifis=0", a data packet is sent as a response to the received token , irrespective o f the setup value of the iitv bit. if "ifis=1" is written , the controller clears the fifo buffer when the fifo buffer does not contain the data that can be sent , and the i n - token is not received in the (micro) frames of each interval set in the iitv bit. it also clears the buffer when the i n - token is not received normally due to bus errors , such as a crc error. the fifo buffer is cleared when the sof packet is received. also , when the sof packet is corrupted, the fifo buffer is cleared when the sof packet is to be received by internal interpolation function. conditions to start the interval counting differ according to the setup value of iitv bit ( s imilar for out) . the f ollowing are the conditions for initialization of the interval counter : (a ) when th is controller is hardware reset ( at this point , the s etup value of the iitv bit is also clear ed to"0") . (b ) when the software writes "aclrm=1". (c ) when the controller detects a usb bus reset .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 66 of 142 jun 28,2013 2.17 pipe c ontrol r egister ? pipe1 control register [pipe1ctr] ? p ipe2 control register [pipe2ctr] ? pipe3 control register [pipe3ctr] ? pipe4 control register [pipe4ctr] ? pipe5 control register [pipe5ctr] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bsts inbufm atrepm aclrm sqclr sqset sqmon pbsy pid 0 0 ? ? ? 0 0 0 0 0 0 ? ? ? 0 0 - - ? ? ? - - - - - - ? ? ? 0 0 bit name function software hardware remarks 15 bsts buffer status the fifo buffer status of the pipe is shown . 0: buffer access i s disabled 1: buffer access is enabled r w 14 inbufm sending buffer monitor when the pipe is transmi tting , the fifo buffer status of the pipe is shown . 0: fifo buffer contains no transmittable data 1: fifo buffer contains transmittable data r w 13 - 11 u n assigned. fix to "0". 10 atrepm auto response mode specifies auto response is disabled/enabled for the pipe . 0: disabled 1: enabled ( a z ero -l ength p acket response while sending, nak response and a nrdy interrupt is issued while receiving) r/w r 9 aclrm auto b uffer c lear mode specifies auto buffer clear mode is disabled/enabled of the pipe. 0: disabled 1: enabled (all buffers are initialized) r/w r 8 sqclr toggle b it c lear specifies "1" while clearing the expected value of the sequence toggle bit in th e next transaction of the pipe, to data0. 0: write i nvalid 1: specifies data0 r(0)/w(1) r 7 sqset toggle b it s et specifies "1" while clearing the expected value of the sequence toggle bit in the next transaction of the pipe, to data1. 0: write iis nvalid 1: specifies data1 r(0)/w(1) r 6 sqmon toggle b it c onfirm sets the expected value of the sequence toggle bit in the next transaction of the pipe. 0: data0 1: data1 r w 5 pbusy p ipe busy sets whether the pipe is being used by the current usb bus. 0: p i pe not used in the usb bus 1: p ipe used in the usb bus r w 4 - 2 un assigned. fix to "0". 1 -0 pid response pid specifies the response method in the next transaction of the pipe. 00: nak response 01: buf response ( maintaining the buffer state) 10: stall res ponse 11: stall response r/w r/w remarks none
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 67 of 142 jun 28,2013 2.17.1 buffer status bit (bsts) this is the bit by which the controller displays whether access from the cpu to the fifo buffer assigned to the pipe is possible. the meaning of this bit differs according to the s etup value of the dir , bfre and dclrm bits. table 2 . 13 bsts b it o perations dir b it setup v alue bfre bit setup v alue dclrm b it setup v alue meaning of bsts bit 0 0 0 set s "1" "when reading of the reception da ta of the fifo buffer is possible" and set s "0" when the data is read completely. 1 this combination cannot be written . 1 0 set s "1" "when reading of the reception data of the fifo buffer is possible" and set s "0" when the software writes "bclr=1" aft er reading the data completely. 1 set s "1" "when reading of the reception data of the fifo buffer is possible " and set s "0" when the data is read completely. 1 0 0 set s "1" "when writing of the transmission data to the fifo buffer is possible" and set s "0" when the data is written completely. 1 this combination cannot be written . 1 0 this combination cannot be written . 1 this combination cannot be written . 2.17.2 sending buffer monitor bit (inbufm) when the pipe is set to transmi t ("dir=1"), the cont roller set s "1" to this bit when the software (or dmac) writes the data on at least one side in the fifo buffer. the controller set s "0" in this bit when all the written data is transmitted from the fifo buffer. when the double buffer is used (if "dblb=1" is written ), "0" is displayed in this bit when the controller has transmitted the data on both the sides and the software (or dmac) has not completely written the data on one side. when the pipe is set to rece ive ("dir=0"), this bit shows a value similar to the bsts bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 68 of 142 jun 28,2013 2.17.3 auto response mode bit (atrepm) w hen the transfer type of thepipe is written to "bulk", "1" can be written to this bit. when "1" is written to this bit, the controller responds as shown below for the token from the usb host . (1) if pip e of bulk - in transfer ( write "type=01" and "dir=1") if writing "atrepm=1" and "pid=buf", the controller sends a zero - length packet for the token. whenever an acknowledgement is received from the usb h ost (if there is one transaction, the token received z ero - l ength packet sent ack received), the controller updates the sequence toggle bit (data - pid). brdy and bemp interrupts do not occur. (2) if pipe of bulk - out transfer (set "type=01" and "dir=0") if writing "atrepm=1" and "pid=buf", the controller se nds a nak response for the out - token (or ping - token) and issues an nrdy interrupt. this bit can be modified when "pid=nak". to modify this bit after modifying the pid bit of the pipe from "buf" to "nak", check that "pbusy=0" and then modify the bit . howev er, when the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit. when writing "1" to this bit t o execute usb communication, the fifo buffer should be empty. while "1" is written to this bit to execut e usb communicati on, do not write to the fifo buffer. if the transfer type of the pipe is isochronous, write "0" to this bit . 2.17.4 auto buffer clear mode bit (aclrm) to delete all content from the fifo buffer allocated to the pipe, write "1" and "0" sequentially in the aclrm bit. when "1" and "0" are written sequentially in this bit, the contents to be cleared by the controller is shown in table 2.14 . moreover, the case when the items need to be cleared is shown in table 2.15 . table 2 . 14 contents c leared by the c ontroller if writing "aclrm=1" no. contents cleared by aclrm bit operation (1) all contents of the fifo buffer allocated to the pipe ( c lear both sides of the fifo buffer while settingto the double buffer) (2) interval count value, if transfer type of the pipe is isochronous table 2 . 15 the necessary case of "aclrm=1" setting s no. instances when clearing the contents is necessary (1) t o clear all content of the fifo buffer allocated to concerned pipe (2) to reset the interval count value (3) wh en modifying the bfre bit s etup value (4) wh en modifying the dblb bit s etup value (5) if there is a forceful termination of transaction count function this bit can be modified when "pid=nak", and when the pipe in the curpipe bit is not written . to m odify this bit after modifying the pipe pid bit from "buf" to "nak", check that "pbusy=0", and then modify it. however, when the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 69 of 142 jun 28,2013 2.17.5 clear bit of sequence toggle bit (sqclr) if the software writes "1" to this bit, the controller writes the expected value of the sequence toggle bit of the pipe to data0. the c ontroller always sets "0" to this bit. not write " 1 " to the sqclr bit except when "pid=nak". to write "1" to this bit after the pid bit of the pipe is modified from "buf" to "nak", check that "pbusy=0" and then modify th e bit. however, when the controlle r has modified the pid bit to "nak", it is not necessary to check the pbusy bit. 2.17.6 write bit of sequence toggle bit (sqset) if the software writes "1" to this bit , the controller sets the expected value sequence toggle bit of the pipe to data1. the controll er always set s "0" to this bit. not write " 1 " to the sqset bit except when "pid=nak". to write "1" to this bit after the pid bit of the pipe is modified from "buf" to "nak", check that "pbusy=0" , and then modify th e bit. however, when the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit. 2.17.7 monitor bit of sequence toggle bit (sqmon) in this bit , the controller displays the expected value of the sequence toggle bit of the pipe. if the selected pipe other than transfe r type isochronous, the controller toggles this bit if the transaction is executed normally. however, this bit is not toggled if there is a data - pid mismatch during reception direction transfer. 2.17.8 p ipe busy bit (pbusy) the controller modifies this bit from "0" to "1" when the usb transaction of the pipe is started. when one transaction is completed, the bit is modified from "1" to "0". when the software has set "pid=nak", possibility of pipe modification can be checked by reading this bit. 2.17.9 r esponse pid b it (pid) for this bit, set a response of the controller in each pipe by the software. the default value of this bit is "nak". while executing a usb transfer by the pipe, modify this bit to "buf". the basic operations (operations when there is no error in the communication packet) of this controller for each setup value of the pid bit are given in table 2.16 . if the pipe is in usb communication, when this bit is modified from "buf" to "nak" by the software, after writing "nak", to check whether the usb transfer of pipe is actually shifted to "nak" status, and check whether "pbusy= 0 ". however, when the controller modifies this bit to "nak", it is not necessary to use the software to check the pbusy bit. in followi ng cases, the controller modifies the value of this bit: (1) when the pipe is receiving and when the software has written "1" to the shtnak bit of the pipe, the controller sets "pid=nak" upon identifying the transfer end. (2) for the pipe, when the data pa cket of payload exceeding the maximum packet size is received, the controller sets "pid=stall(11)". (3) w hen the usb bus reset is detected, the controller sets "pid=nak". write "10" to shift from "pid=nak("00")" status to "pid=stall" status. write "11" t o shift from buf("01") status to stall status. first write "10" and then write "00" to shift form "stall(11)" to nak status. first, shift to nak status and then to buf status to shift from stall status to buf status.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 70 of 142 jun 28,2013 table 2 . 16 list of c ontroller o perations a ccording to the pid bit pid b it setup v alue transfer type (type b it setup v alue) transfer d irection (dir b it setup v alue) controller o perations "00 (nak)" bulk ("type=01") or interrupt ("type=10") n ot de pend ent on s etup value nak response is sent to the token from the usb h ost . however, when "atrepm=1", operations mentioned in 2.17.3 are executed. isochronous ("type=11") rece ive ("dir=0") does not respond to the token from the usb h ost transmi t ("dir=1") a zero - length packet is sent to the usb host pipe use disabled ("type=00") n ot depend ent on s etup value does not respond to the token from the usb h ost "01 (buf)" bulk ("type=01") rece ive ("dir=0") when an out token is sent from the usb host, if the fifo buffer for the selected pipe is in the receive - enabled state, the data is received and an ack or nyet response is returned. if not, a nak response is returned. when a ping token is sent from the usb host , if the fifo buffer of the selected pipe is in the receive - enabled state, an ack response is returned. if not, a nak response is returned. interrupt ("type=10") rece ive ("dir=0") for the o ut - token from the usb h ost, if the fifo buffer of the pipe is in receive enabled status, the data is received and an ack response is sent. otherwise the nak response is sent. bulk ("type=01") or interrupt ("type=10") transmi t ("dir=1") if the corresponding fifo buffer is in send possible status, the data is sent for the token from the usb. otherwise a nak response is sent. isochronous ("type=11") rece ive ("dir=0") for the o ut - token from the usb h ost, if the fifo buffer of the pipe is in receive enabled status, the data is received. otherwise, the data is deleted. transmi t ("dir=1") if the corresponding fifo buffer is in send possible status, the data is sent for the token from the usb. otherwise , a zero - length packet is sent. "10 (stall)" or "11 (stall)" bulk ("type=01") or interrupt ("type=10") n ot depend ent on s etup value a stall response is sent to the token from the usb h ost . isochronous ("type=11") n ot depend ent on s etup value does not respond to the token from the usb h ost .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 71 of 142 jun 28,2013 ? pipe6 control register [pipe6ctr] ? pipe7 control register [pipe7ctr] ? pipe8 control register [pipe8ctr] ? pipe9 control register [pipe9ctr] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bsts ac lrm sqclr sqset sqmon pbsy pid 0 ? ? ? ? ? 0 0 0 0 0 ? ? ? 0 0 - ? ? ? ? ? - - - - - ? ? ? 0 0 bit name function software hardware remarks 15 bsts buffer status fifo buffer status of the pipe is displayed. 0: buffer access is disabled 1: buffer acc ess is enabled r w 1 4 - 10 un assigned. fix to "0". 9 aclrm auto buffer clear mode specifies auto buffer clear mode disable/enable of the pipe . 0: disabled 1: enabled (all buffers are initialized) r/ w r 8 sqclr toggle bit clear specifies "1" while clear ing the expected value of the sequence toggle bit in the next transaction of the pipe to data0. 0: invalid 1: specifies data0 r(0)/ w(1) r 7 sqset toggle bit set specifies "1" while clearing the expected value of the sequence toggle bit in the next trans action of the pipe to data1. 0: invalid 1: specifies data1 r(0)/ w(1) r 6 sqmon toggle bit confirm set s the expected value of the sequence toggle bit in the next transaction of the pipe. 0: data0 1: data1 r w 5 pbusy p ipe busy displays whether the pipe is being used by the current usb bus. 0: p ipe not used in the usb bus 1: p ipe used in the usb bus r w 4 - 2 un assigned. fix to "0". 1 -0 pid response pid specifies the response method in the next transaction of the pipe. 00: nak response 01: buf response (in keeping with the buffer state) 10: stall response 11: stall response r/w r/w remarks none
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 72 of 142 jun 28,2013 2.17.10 buffer status bit (bsts) refer to 2.17.1 . 2.17.11 auto buffer clear mode (aclrm) to delete all content from the fifo buffer allocated to the pipe, write "1" and "0" sequentially in the aclrm bit. when "1" and "0" are written sequentially to this bit, the contents to be cleared by the controller is shown in table 2.17 . m oreover, the cases when the items need to be cleared is shown in table 2.18 . table 2 . 17 c ontents cleared by the controller if writing "aclrm=1" no. contents cleared by aclrm bit operation (1) all content fro m the fifo buffer allocated to the pipe table 2 . 18 the necessary case of "aclrm=1" settimgs no. instances when clearing the contents is necessary (1) t o clear all content of the fifo buffer allocated to con cerned pipe (2) to reset the value of interval count (3) while modifying the bfre bit s etup value (4) if there is a forceful termination of transaction count function this bit can be modified when "pid=nak", and the pipe in the curpipe bit is not wri tten . to modify this bit after m odify ing the pid bit of the pipe from "buf" to "nak" check that "pbusy=0", and modify th e bit. however, when the controller has modified the pid bit to "nak", it is not necessary to check the pbusy bit. 2.17.12 clear bit of sequenc e toggle bit (sqclr) refer to 2.17.5 . 2.17.13 set bit of sequence toggle bit (sqset) refer to 2.17.6 . 2.17.14 monitor bit of sequence toggle bit (sqmon) refer to 2.17.7 . 2.17.15 p ipe busy bit (pbusy) refer to 2.17.8 . 2.17.16 response pid bit (pid) refer to 2.17.9 .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 73 of 142 jun 28,2013 2.18 transaction counter ? pipe1 transaction counter enabled register [pipe1tre] ? pipe2 transaction counter enabled register [pipe2tre] ? pipe3 transaction counter enabled register [pipe3tre] ? pipe4 transaction counter enabled register [pipe4tre] ? pipe5 transaction counter enabled register [pipe5tre] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 trenb trclr ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? - - ? ? ? ? ? ? ? ? bit name function software hardware remarks 15 - 10 un assigned. fix to "0". 9 trenb transaction counter enabled specifies whether the transaction counter is invalid/valid. 0: transaction counter function invalid 1: transaction counter function valid r/w r 8 trclr transaction counter clear transaction cou nter can be cleared to "0" by writing "1" to this bit . 0: invalid 1: count counter clear r(0)/w(1) r 7 - 0 un assigned. fix to "0"." remarks * not m odify each bit of the register except when "pid=nak". to modify each bit after modifying the pid bit of the pipe from "buf" to "nak", check that "pbusy=0", and then modify it . however, when the controller modifies pid bit to "nak", it is not necessary to check the pbusy bit. 2.18.1 transaction counter enabled bit (trenb) for the reception pipe, after the total number of packets is written to the trncnt bit using the software, the controller executes the following control on receiving the same number of packets as the s etup value of the trncnt bit : (1) when the continuous transmission/reception mode is used ( write "cnt md=1"), toggles on cpu side even if the fifo buffer is not full when reception is completed. (2) if writing " shtnak=1" , modifies the pipe pid bit to "nak". (3) if writing "dende=1" and "pktmd=0", asserts the dend signal while reading the last data. (4) if writing " bfre=1" , asserts the brdy interrupt. regarding the transmission pipe, write "0" to this bit . when the transaction count function is not used, write "0" to this bit. when the transaction count function is used, set the trncnt bit before writing "1 " to this bit . also write "1" to this bit before receiving the initial packet that is the transaction target. 2.18.2 transaction counter clear bit (trclr) if the software writes "1" to this bit , the controller clears the current count value of the transaction co unter corresponding to the pipe and set s "0" in this bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 74 of 142 jun 28,2013 ? pipe1 transaction counter register [pipe1trn] ? pipe2 transaction counter register [pipe2trn] ? pipe3 transaction counter register [pipe3trn ? pipe4 transaction counter register [pipe4trn] ? pip e5 transaction counter register [pipe5trn] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 trncnt 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - bit name function softw are hardware remarks 15-0 trncnt transaction counter transaction counter i f write: specifies the total number of reception packets (number of transaction s) to be received by the selected pipe. if read: if "trenb=0": displays t he written transaction counte r i f "trenb=1 " : displays the t ransaction counter during the count r/w r/w remarks 2.18.3 transaction counter bit (trncnt) for the reception pipe, after the total number of packets is written to this bit using the software, if "1" is written to the trenb bi t, the controller executes the control mentioned in 2.18.1 . if "trenb=0", the controller show s the number of transaction written by the software to this bit. if "trenb=1", the controller show s the number of tran saction in the count in this bit. the controller increases the trncnt bit by one, when the following conditions are fulfilled in the status at the time of reception : (a) "trenb=1" (b) (trcnt written value current number of transaction +1) while receivin g the packet (c) the payload of the received packet matches the written value of the mxps bit when the controller fulfill s one of the following conditions ((1) - (3)), the trncnt bit is cleared to "0". (1) when all the following conditions are fulfilled : (a) "trenb=1" (b) w hile receiving the packet ( trcnt s etup value = current value +1) (c) the payload of the received packet matches with the s etup value of mxps bit (2) when both of the following conditions are fulfilled : (a) "trenb=1" (b) a short packet is received (3) when both of the following conditions are fulfilled : (a) when the software writes " 1 " to the trclr bit for the t ransmission pipe, write "0" to this bit. when the transaction count function is not used, write "0" to this bit. this bit ca n be modified when "pid=nak" and "trenb=0". to modify this bit after m odify ing the pipe pid bit from "buf" to "nak" check that "pbusy=0", and modify th e bit. however, when the controller has modified the pid bit to "nak", it is not necessary to check the p busy bit . wh en modifying the bit value, write "trc lr =1" before writing "trenb=1".
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 75 of 142 jun 28,2013 3 operating instructions 3.1 system controls and oscillation controls this chapter provides instructions concerning register operations necessary to initialize the r8a6659 3 cont roller and descriptions of the registers necessary to control power consumption. 3.1.1 reset table 3.1 shows the list of the various resets related to this controller. please refer to ? chapter 2. registers ? for a descri ption of the register initialization status after each reset operation. table 3 . 1 reset list name operation h/w reset ? l ? level input from rst_n pin usb bus reset this controller detects reset automatically from d+/d - line status 3.1.2 bus interface setting table 3.2 shows the parameters for the controller bus interface that must be set before enabling ( ? xcke = 0 ? ) the oscillation buffer operation. make sure these are se t immediately after the h/w reset. table 3.3 shows the parameters to be set after the oscillation buffer operation is enabled (? xcke = 1 ? is set and controller is in ? scke = 1 ? status). table 3 . 2 bus interface settings (set before clock supply starts) register name bit name setting description pincfg ldrv specify drive current controls pincfg inta set int_n pin polarity table 3 . 3 bus interface settings (set after clock supply starts) register name bit name setting description syscfg1 pcsdis specify include/exclude cs_n assert in recovery conditions from low power sleep state syscfg1 lpsme specify enable/disable for low power sleep state dmaxcfg dreqa set dreqx_n pin polarity dmaxcfg dacka set dackx_n pin polarity dmaxcfg denda set dendx_n pin polarity dmaxcfg obus set obus mode sofcfg brdym set pipebrdy interrupt status clear timing sofcfg intl set int_n pin outpu t sense x = 0 or 1 3.1.3 clock supply control the clock supply to the controller usb block is started by selecting the xin pin input clock in the syscfg 0 register xtal bit and enabling the oscillation buffer in the xcke bit by software. confirm by software th at the scke bit is set to ?1 ? , then proceed with the next process.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 76 of 142 jun 28,2013 3.1.4 usb block operation enable after clock supply has started to the usb block ( ? scke = 1 ? ), set the syscfg 0 register usbe bit to ? 1" with software to enable usb block operations . 3.1.5 hi - speed operation enable bit setting and usb transmission speed determination when the hi - speed operation is enabled, set the hi - speed operation enable bit ( syscfg 0 register hse bit) to ?1 ? after setting the controller function selection bit. if operating the co ntroller only at full - speed, set the syscfg 0 register hse bit to ?0 ?. when hi - speed operation is enabled, the controller executes the reset handshake protocol and automatically determines the usb transmission speed. the result of the reset handshake is sho wn in the dvstctr 0 register rhst bit. 3.1.6 usb transmission speed control table 3.4 shows the corresponding usb transmission speeds. table 3 . 4 controller function select ion table settings function and transmission speed hse speed remarks 0 full operates at full - speed 1 hi or full operates at hi - speed when reset handshake protocol (rhsp) is successful , at full - speed when rshp is not successful . 3.1.7 usb data bus pull - up settings this controller has built - in pull - up resistance for the d+ line. power supply for the d+ pull - up is avcc . a fter the connection to the usb host is confirmed, set syscfg 0 register dprpu bit to ?1 ? and pull - up d+. in addition, the controller has b uilt - in d+/d - line terminating resistance for hi - speed transmissions and output resistance for full - speed transmissions. the controller automatically switches the built - in resistance after connection to the usb host upon the execution or detection of a res et handshake, suspend, or resume event. when the syscfg 0 register dprpu bit is set to ? 0 ? in the usb host attached status, the controller disables the usb d+ line pull - up (or d+, d - line termination). therefore, software can be used to create the usb cable detached status when viewed from the usb host.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 77 of 142 jun 28,2013 3.1.8 power - consumption control 3.1.8.1 power consumption control outline the r8a6659 3 controller offers two types of low - consumption power supply: low power sleep state and vcc - off state. table 3.5 provides a description of each low - power consumption state. figure 3.1 shows a diagram of the controller status transitions. table 3 . 5 low power consumption states controller state description low power sleep state the controller transitions to the low - power sleep state when ? lpsme=1 ? is set during initialization, and the clock is stopped in the current controller operation state (refer to 3.1.9.2 ). the value of each register is maintained, but the contents of the fifo buffer are not saved. vcc - off state the controller can be transitioned to the vcc - off state by turning off only vcc while keeping vif on. this state r educes power consumption even further than that of the low - power sleep state. the values in the registers are not saved. initialized state after h/w reset normal operating state initialization (when ? attach ? etc. is detected) h/w reset vcc or avcc off (vif remains on) only vcc off (vif remains on) vcc, avcc on vcc, avcc, vif on low - power sleep state vcc off state stop clock sequence completed r ecovery event *1) 1) recovery event: cs_n signal is asserted by cpu dummy read when ? pcsdis=1 ? or detection of resm interrupt when ? rsme=1 ? , or detection of vbint interrupt when ? vbse=1 ? . figure 3 . 1 controller state transition diagram
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 78 of 142 jun 28,2013 3.1.8.2 low - p ower sleep state when syscfg1 register lpsme bit is set to ? 1 ? in the controller initialization , if the clock stop process is executed while the controller is in the normal operating state, the controller goes to the low - power sleep state. in this state, p ower consumption is reduced while maintaining the value of each register . if the controller is transitioned to this state during usb suspend, power consumption can be reduced while still maintaining the usb address, device state, and other information. ple ase refer to 3.1.9.2 and figure 3.3 for the detailed the setup sequence to transition to the low - power sleep state. to return from the low - power sleep state, refer to table 2 . 6 . the return sequence is detailed in 3.1.9.3 and figure 3.4 . the controller automatically enables the oscillation buffer operation when it detects a recovery condition from the low - power sleep state. at this time, the value of the xcke bit is not changed. the user must confirm ? scke=1 ? by software and then set ? xcke=1 ?. to enable the low - power sleep state, set the syscfg 1 register lpsme bit to ?1 ? during controller ini tialization. registers cannot be accessed during the low - power sleep state. in addition, data in the fifo buffers will be lost during the transition, so make a send/receive data process is executed before transitioning to the low - power sleep state. 3.1.8.3 vcc o ff state the vcc off state allows some power to be supplied to the controller but cuts off supply to the usb block. the controller is transitioned to the vcc off state by keeping the vif on while turning off the vcc and avcc. unlike returning the control ler from the low - power sleep state by controlling the registers with software, this state requires the vcc and avcc to be turned on and an h/w reset executed. the contents of each register are lost when the vcc is turned off, and the controller goes to the initialization state after recovery.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 79 of 142 jun 28,2013 3.1.9 state transition timing 3.1.9.1 start of internal clock supply (from h/w reset state to normal operating state) figure 3.2 shows a diagram of the clock supply start control timing f or the controller. when transitioning from the h/w reset state or the clock stopped state to the normal operating state, handle the bits according to the timing below. (1) enable oscillation buffer ? xcke=1 ? (2) software wait until ? scke=1 ? . (controller automatic ally enables pllc and scke .) xcke pllc(h/w) scke(h/w) (1) (2) start internal clock supply start process figure 3 . 2 clock supply start control timing diagram 3.1.9.2 internal clock supply stop (setup sequence to transition from normal operating state to low ? p ower sleep state) figure 3.3 shows the control timing diagram for transitioning the controller from the normal operating state to the low - power sleep state. to enable the low - power sleep state, set ? lpsme=1 ? in the initialization. (1) confirm sofcfg register edgests bit, then use software wait until ? edgests=0 ?. (2) stop internal clock supply ? scke=0 ? (3) software wait until internal clock stops. (requires 60ns or more wait) (4) stop pll. ? pllc=0? (5) stop oscillation buffer oper ation ? xcke=0 ? pllc scke (3) min 60ns (2) start (4) (5) xcke figure 3 . 3 internal clock supply stop process timing diagram
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 80 of 142 jun 28,2013 3.1.9.3 restart internal clock supply (from low - power sleep state to normal operating state) figure 3.4 shows a diagram for transition from the low - power sleep state to the normal operating state. (1) interrupt is generated to trigger recovery from low - power sleep state, int_n pin is asserted. (or, a dummy is executed by software and the controller is returned to the normal state *3) ). oscillation buffer is enabled but does not affect the xcke bit. (2) software wait for 1ms. (do not access the controller during this time.) (3) software wait until ? sck e=1 ? . (controller automatically starts the oscillation buffer and enables pllc and scke .) (4) set ? xcke=1 ? with software. *3) return from the low - power sleep state can be enabled by accessing the cpu if syscfg 1 register pcsdis bit is set to ?0 ? . if returning to t he normal state in these conditions, int_n is not asserted. figure 3 . 4 control timing diagram for returning from low - power sleep state
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 81 of 142 jun 28,2013 3.2 interrupt functions 3.2.1 interrupt function o utline table 3.6 shows a list of controller interrupt functions. table 3 . 6 interrupt function list bit interrupt name interrupt detection conditions [usage instructio ns] related status refer - ence vbint vbus interrupt when change in vbus input pin status is detected (low to high or high to low):[detects host connect/disconnect.] vbsts 2.11.1 resm resume interrupt when cha nge in usb bus is detected in suspend state (j - state to k - state, j - state to seo state):[detects resume.] - 2.11.2 sofr frame number update interrupt when sof packet with different frame number is sent - 2.11.3 3.2.8 dvst device state transition interrupt when transition in device state is detected: detects usb bus reset detects suspend state r eceives set address request receives set configuration request dvsq 2.11.4 3.2.6 ctrt control transfer stage transition interrupt when transition in contro l transfer stage is detected: completes setup stage transitions to control write transfer status stage transitions to control read transfer status stage completes control transfer generates control transfer sequence error ctsq 2.11.5 3.2.7 bemp buffer empty interrupt when all data in buffer memory is sent and buffer is empty when a packet is received that is bigg er than maxpacket size pipebemp 2.11.6 2.11.11 3.2.5 nrdy buffer not ready interrupt token is received when ? pid=buf ? is set and buffer memory is in a state that does not allo w transfers crc error or bit stuff error occurs during isochronous data receive i nterval error occurs during isochronous data receive pipenrdy 2.11.7 2.11.10 3.2.4 brdy buffer ready interrupt when fifo buffer goes to ready (read or write enabled state) pipebrdy 2.11.8 2.11.9 3.2.3 table 3.7 shows the controller int_n pin operation. if various interrupt factors are generated, the int_n pin output method can be set through the sofcfg register intl bi t. also, the int_n pin active state can be set by the pincfg register inta bit. set the int_n operation to meet user system specifications. table 3 . 7 int_n pin operation int_n pin operation intl setting for one type of interrupt factor for various types of interrupts factors edge sense (? intl=0 ?) asserted until interrupt factor is released (interrupt status is cleared or interrupt enable bit is set to ? disabled ? ). negated for 32 clock period at 48mhz when one interrupt factor is released. level sense ( ? intl=1 ? ) asserted until interrupt factor is released. asserted until all interrupt factors are released. active level: low when ? inta=0 ? , high when ? inta=1 ?
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 82 of 142 jun 28,2013 interrupt factor 1 interrupt factor 2 i nt_n pin (1) edge sense generate factor 1 generate factor 2 clear factor 1 clear factor 2 negate period 1 interrupt factor 1 interrupt factor 2 i nt_n pin (2) level sense generate factor 1 generate factor 2 clear factor 1 clear factor 2 *1) when factor 1 interrupt enable bit is disabled in stead of factor 1 being cleared, the negate period is not generated. figure 3 . 5 int_n pin operating diagram (example when ? inta=0 ? is set)
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 83 of 142 jun 28,2013 figure 3.6 shows the interrupt configurations for the controller.. int_n edge / level generated circuit intenb0 intsts0 dvst dvse vbint vbse resm rsme sofr sofe ctrt ctre bemp bempe nrdy nrdye brdy brdye detect usb bus reset detect set_address detect set_configuration detect suspend end control transfer data stage data stage e rror setup receive control write control read control transfer contro l transfer b9 b1 b0 b0 b1 b9 ... ... ... b9 b1 b0 b0 b1 b9 ... ... ... b9 b1 b0 b0 b1 b9 ... ... ... bemp interrupt enable register nrdy interrupt enable register brdy interrupt enable register bemp interrupt status register nrdy interrupt status register brdy interrupt status register figure 3 . 6 interrupt configuration diagram
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 84 of 142 jun 28,2013 3.2.2 operations and cautions for clock stopped state vbint and resm interrupt factors will be generated even when the clock is stopped (including low - power sleep state) and, when enable d in the interrupt enable register, the interrupt from the int_n pin will be asserted. clear the interrupt factors after executing the clock supply start process. 3.2.3 brdy interrupt the brdy interrupt conditions are shown in 2.11.9 . figure 3.7 shows the diagram of the brdy interrupt generation timing. when a zero - length packet is received, the corresponding bit of the brdysts register goes to ?1 ? but the data of the corre sponding packet cannot be read. clear the buffer ( ? bclr=1 ? ) after clearing the brdysts register. in addition, interrupts can be generated in transfer units in pipe1 to pipe9 when using dma transfers in the read direction by setting the pipecfg register bfr e bit to ?1 ?. (1) example of zero - length packet receive or data packet receive when bfre=0 (single buffer s etting) token packet usb bus ack handshake (2) data packet receive when bfre=1 (single buffer setting) token packet usb bus (3) example of packet send (single buffer setting) token packet data packet usb bus ack handshake brdy interrupt ( change in corresponding pipebrdy bit) buffer memory is read enabled *2 and bdry interrupt is generated buffer memory is read enabled and bdry interrupt is generated transfer is completed *3 and brdy interrupt is generated packet sent by host packet sent by peripheral fifo buffer status *1) ack handshake is not existing in isoc hro no us transfers *2) conditions for fifo buffer to be read - enabled: one of the following read events is generated when no unread data remains in the cpu buffer memory (1) 1 packet received in non - continuous transfer mode, or (2) one of the following receive events in the continuous transfer mode (a) receive short packet (incl. zero - length) (b) buffer f ull occurs (c) receive packets equal to number of packets in transaction counter *3) transfer complete conditions: when one of the following receive events occurs (1) receive short packet (incl. zero - length), or (2) receive packets equal to number of packets in transaction counter fifo buffer status zero - length packet / short data packet / data packet (maximum size) zero - length packet / short data packet / data packet (maximum size) fifo buffer status buffer memory is read enabled *2 *1) ack handshake *1) *1) brdy interrupt ( change in corresponding pipebrdy bit) brdy interrupt ( change in corresponding pipebrdy bit) receive - enabled state read - enabled state receive - enabled state read enabled st ate send - enabled state w rite - enabled state figure 3 . 7 brdy interrupt generation timing diagram
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 85 of 142 jun 28,2013 the conditions needed for the controller to clear the intsts0 register brdy bit vary depending on the set value of the sofcfg register brdym bit. table 3.9 shows the conditions needed to clear the brdy bit. table 3 . 8 conditions for brdy clear by controller brdym brdy bit clear conditions 0 when all bits of the brdyst s register are cleared by software, the controller clears the intsts0 register brdy bit. 1 when the bsts bit of all pipes go to ?0?, the controller clears the intsts0 register brdy bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 86 of 142 jun 28,2013 3.2.4 nrdy interrupt the nrdy interrupt conditions are shown in 2.11.10 . figure 3.8 shows the diagram of the nrdy interrupt generation timing. (*1 (*1 (crc bit, etc ) *3 (2) data receive; out token receive example (single buffer setting) in token packet out token packet nak handshake data packet usb bus usb bus ping packet nak handshake usb bus nrdy interrupt (change in corresponding pipenrdy bit) * 2 (3) data receive; ping token receive example (single buffer setting) (1) data send example (single buffer setting) nrdy interrupt (change in corresponding pipenrdy bit) *2 nrdy interrupt (change in corresponding pipenrdy bit) *2 *1) handshake is not existing in is ochronous transfers. *2) pipenrdy bit is only changed to ? 1 ? when target pipe pid bit is set to ? 1 ? . *3) crc bit and ovrun bit are changed only when target pipe transfer type is isochronous. buffer memory statu s buffer memory status buffer memory status w rite - enabled status (no send - enabled data) read - enabled status (no receive - enabled area) read - enabled status (no receive - enabled area) nak handshake packet sent by host packet sent by peripheral figure 3 . 8 nrdy interrupt generation timing
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 87 of 142 jun 28,2013 3.2.5 bemp interrupt the bemp interrupt conditions are shown in 2.11.11 . figure 3.9 shows the diagram of the bemp interrupt generation timing. (*1 (*1 (1) data send example (2) data receive examp le in token packet out token packet ack handshake data packet stall handshake data packet (maximum packet size over) usb bus usb bus bemp interrupt (change in corresponding pipebemp bit) bemp interrupt (change in corresponding pipebemp bit) packet sent by host packet sent by peripheral buffer memory status w rite - enabled status (no send - enabled data ) *1) handshake is not existing in isochronous transfers. send - enabled status figure 3 . 9 bemp interrupt generation timing diagram
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 88 of 142 jun 28,2013 3.2.6 device state transition interrupt figure 3.10 provides a diagram of r8a6659 3 device state transitions . the controller manages the device state and generates the device state transition interrupt. however, return from the suspend state (resume signal detection) is detected by the resume interrupt. the device state transition interrupt can be enabled or disabled by setting the intenb0 register. the device state transition can be confirmed using the intsts0 register dvsq bit. when transitioning to the default state, the device state transition interrupt is generated after the reset handshake protocol is completed. powered state (dvsq="000") detect suspend (dvst=?1?) resume (resm= ?1? ) detect usb bus reset (dvst=?1?) execute setaddress ( address= 0 ) (dvst= ? 1 ? ) detect usb bus reset (dvst=?1?) default state (dvsq="001") address state (dvsq="010") configured state (dvsq="011") suspended state (dvsq="100") suspended state (dvsq=" 101") suspended state (dvsq="1 1 0") suspended state (dvsq="1 11 ") detect suspend (dvst=?1?) resume (resm=?1?) execute setaddress ( address >0 ) (dvst= ? 1 ? ) detect suspend ( dvst= ? 1 ?) resume (resm=?1?) detect suspend (dvst=?1?) resume (resm=?1?) execute set configuration (configurationvalue = 0 ) (dvst= ? 1 ? ) execute se t configuration (configurationvalue != 0 ) (dvst ? 1 ? ) note: solid line transitions indicate the dvst bit will be set to ? 1 ? . dotted line transitions indicate the resm bit will be set to ? 1 ? . figure 3 . 10 device state transitions
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 89 of 142 jun 28,2013 3.2.7 control transfer stage transition interrupt figure 3.11 shows a diagram of the control transfer stage transition. the co ntroller manages the control transfer sequence and generates the control transfer stage transition interrupt. the control transfer stage transition interrupts can be enabled or disabled individually in the intenb0 register. the transitioned transfer stage can be confirmed in the intsts0 register ctsq bit. the control transfer sequence is as follows. when an error occurs, the dcpctr register pid bit goes to ?1x ? (stall). (1) control read transfer (a) out or ping token is received before any data transfer occurs cor responding to the data stage in token (b) in token is received in the status stage (c) the data packet received in the status stage is a ?datapid=data0? packet (2) control write transfer (a) in token is received before any ack response is sent corresponding to a data stag e out token (b) the first data packet received in the data stage is a ?datapid=data0? packet (c) out or ping token is received in the status stage (3) no - data control transfer (a) out or ping token is received in the status stage note that in the control write transfer d ata stage, if the number of receive data is more than the usb request wlength value, the control transfer sequence error cannot be recognized. also, in the control read transfer status stage, when a packet other than a zero - length packet is received, an ac k response is returned and the transfer is successfully completed. when a ctrt interrupt ( ? serr=1 ? setting) is generated due to a sequence error, ? ctsq=110? value is stored until ? ctrt=0 ? is written by software (interrupt status clear). therefore, because ? ctsq=110? is being maintained, the ctrt interrupt for the completion of the setup stage is not generated, even when a new usb request is received. events occurring after the setup stage are saved by the controller and a ctrt interrupt is generated after t he interrupt status is cleared by software . send ack receive ack send ack detect error receive setup token send ack send ack "ctsq = 0 11" control write data stage "ctsq = 100" control write status stage "ctsq = 000" idle stage "ctsq = 101" no - d ata co ntro l status stage out to ken in token receive ack 1 1 3 4 "ctsq = 000" setup stage "ctsq = 001" control read d ata stage "ctsq = 010" control read status stage 2 1 4 "cts q = 110" control transfer sequence error 5 ctrt interrupt ? setup stage end ? control read transfer status stage t ransition ? control write transfer status stage transition ? control transfer complete ? control transfer sequence error receive setup token receive setup token when all stages within box detect errors, the received setup token is valid. figure 3 . 11 control transfer stage transition
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 90 of 142 jun 28,2013 3.2.8 frame number update interrupt figure 3.12 sh ows an example of the r8a6659 3 sofr interrupt output timing. w hen the controller detects a new sof packet in full - speed operation, it updates the frame number and generates an sofr interrupt. in hi - speed operation , when an sof packet with a different fram e number is detected after the controller goes to the sof lock state, the controller updates the frnm bit and generates the sofr interrupt. the sof interpolation function also runs in hi - speed operation after going to the sof locked state. the sof locke d state means that two sof packets with different frame numbers are received without errors. the sof lock monitor start and stop conditions are as follows. (1) sof lock monitor start conditions "usbe=1" and internal clock is supplied (2) sof lock monitor sto p conditions "usbe=0", usb bus reset is received, or suspend is detected sof falling sof falling sof falling sof falling (1) e xample of sofr interrupt generated after sof lock sof packet sof number frame number (frnm bit) sofr interrupt (2) e xample of sofr interrupt generated before sof lock sof packet sof number sofr interrupt sof lock 7 0 1 6 7 0 7 0 1 7 0 1 2 7 0 1 no interrupt output due to no lock 7 0 1 2 3 6 7 0 1 2 3 4 5 6 6 7 0 1 3 4 6 interrupt output by sof interpolation function 4 5 sof falling sof interpolation generated sof interpolation generated sof interpolation not generated sof interpolation not generated sof interpolation generated no interrupt output due to no lock interrupt output by sof interpolation function frame nu mber ( frnm bit) 0 (value before sof lock) 4 6 figure 3 . 12 sofr interrupt output timing example
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 91 of 142 jun 28,2013 3.3 pipe control t able 3.9 provides a list of pipe settings for the controller. in usb data transfers, data transmission is executed in logic pipes called endpoints. the r8a6659 3 controller comes with nine pipes for data transfer. each pipe can be set to meet the requireme nts of the user system. table 3 . 9 pipe settings register name bit name setting description comments pipesel pipesel specifies the pipe number for setting the pipebu, pipemaxp, pipeperi registers refer to 2.16.1 more details. . dcpcfg pipecfg type specifies the transfer type refer to 2.16.2 for more details. bfre selects brdy interrupt mode pipe1 - 5: can be set refer to 2.16.3 , 3.4.3.4 , and 3.4.3.5 for more details. dblb selects single or double buffer pipe1 - 5: can be set refer to 2.16. 4 and 3.4.1.4 for more details. cntmd selects continuous transfer or non- continuous transfer pipe1 - 2: can be set (in bulk transfer setting only) pipe3 - 5: can be set for continuous send/receive, set the buffer size in multiples of the payload. refer to 2.16.5 and 3.4.1.5 for more details. dir selects transfer direction (read or write) set to in or out refer to 2.16.7 and 3.4.2.1 for more details. epnum endpoint number refer to 2.16.8 for more details. shtnak disables pipe when transfer is completed. dcp: can be set pipe 1 - 2: can be set (in bulk transfer setting only) pipe 3 -5: can be set refer to 2.16.6 for more details. pipebuf bufsize buffer memory size dcp: cannot be set (fixed at 256 bytes) pipe1 - 5 can be set (set in 64 byte units up to a max of 2k b ytes) pipe6 - 9: cannot be set (fixed at 64 bytes) refer to 2.16.9 and 3.4.1 for more details. bufnmb buffer memory number dcp: cannot be set (fixed at areas 0 - 3) pipe1 - 5: can be set ( between areas 8 and 135 (0x87) pipe6 - 9: cannot be set (fixed at areas 4- 7) refer to 2.6.10 and 3.4.1 for more details. dcpmaxp pipemaxp mxps maximum packet size refer to 2.16.11 and 3.3.1 for more details. pipeperi ifis buffer flash pipe1 - 2: can be set (in isochronous transfer setting only) pipe3 - 9: cannot be set refer to 2.16.12 and 3.9.5 for more details. iitv interval counter pipe1 - 2: can be set (in isochronous transfer setting only) pipe3 - 9: cannot be set refer to 2.16.13 and 3.9.3 for more details. dcpctr pipexctr bsts buffer s tatus refer to 2.17.1 and 3.4.1.1 for more details. inbufm in buffer monitor refer to 2.17.2 and 3.4.1.1 f or more details. atrepm auto response mode pipe1 - 5: can be set aclrm auto buffer clear can be enabled and disabled when buffer memory is read - enabled refer to 2.17.4 and 2.17.11 for more detail s. sqclr sequence toggle bit clear clear data toggle bit refer to 2.17.5 and 3.3.4 for more details.. sqset sequence toggle bit set set data toggle bit refer to 2.17.6 and 3.3.4 for more details. sqmon sequence toggle bit confirm confirm data toggle bit refer to 2.17.7 and 3.3.4 for more details. pbusy confirm pipe busy refer to 2.17.8 for more details. pid response pid refer to 2.17.9 and 3.3.2 for more details..
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 92 of 142 jun 28,2013 register name bit name setting description comments pipextre tren b transaction count enable pipe1 - 5: can be set refer to 2.18. 1 for more details. trclr current transaction counter clear pipe1 - 5: can be set refer to 2.18.2 for more details. pipextrn trncnt transaction counter pipe1 - 5: can be set refer to 2.18.3 for m ore details. 3.3.1 maximum packet size setting maximum packet size for each pipe is set in the mxps bit of the dcpmaxp and pipemaxp registers. dcp and pipes 1 - 5 can be set with any maximum packet size defined in the usb specifications. pipes 6- 9 are limited t o maximum packet size of 64 bytes. set the maximum packet size before starting transfers (set ? pid=buf ?). dcp: set to ?64? for hi - speed operation dcp: set to ?8 ?, ? 16?, ? 32? , or ? 64? for full - speed operation pipe 1 - 5: set to ? 512 ? for hi - speed bulk transf er pipe 1 - 5: set to ?8 ?, ? 16?, ? 32? , or ?64? for full - speed bulk transfer pipe 1 - 2: set a value from ?1 ? to ? 1024? for hi - speed isochronous transfer pipe: 1 - 2: set a value from ?1 ? to ? 1023? for full - speed isochronous transfer . for more details, see sectio n 3.9 . pipe 6 - 9: set a value from ?1 ? to ?64?. high - bandwidth transfers are not yet supported in interrupt and isochronous transfers. 3.3.2 response pid set the response pid for each pipe with the pid bit of the dc pctr and pipexctr registers. the response pid specifies the response to a transaction from the host. (a) nak setting: always sends a nak response when a transaction is issued. (b) buf setting: responds to the transaction in accordance with the buffer memory statu s. (c) stall setting: always sends a stall response when a transaction is issued. regardless of the value set in the pid bit, an ack is always sent as a response to a setup transaction and the usb request is stored in corresponding registers. based on the res ults of the transaction, the controller may trigger the pid bit to be written. the controller will trigger a write event to the pid bit in the following cases. (a) nak setting: (i) when setup token is received normally (only dcp) (ii) in bulk transfers when pipecfg re gister shtnak bit is set to ?1? and short packet is received (iii) in bulk transfers when shtnak bit is set to ?1? and the transfaction counter is completed. (b) buf setting: the buf cannot be written by the controller (c) stall setting: (i) when a maximum packet size over error is detected for a received data packet (ii) when a control transfer sequence error is detected
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 93 of 142 jun 28,2013 3.3.3 pipe information modification process the following pipe control register bits can be re - written only when usb transmission is disabled ( ? pid=nak ? ). figure 3.13 shows the process for switching the pipe control register from the usb transmission enabled status. registers that are prohibited setting when the usb transmission is enabled ( ? pid=buf ?): (1) all bits of dcpcfg and dcpmaxp registers (2) dcpctr register sqclr , sqset , and csclr bits (3) all bits of pipecfg , pipebuf , pipemaxp and pipeperi registers (4) pipexctr register atrepm , aclrm , sqclr , and sqset bits (5) all bits of pipextre and pipextrn registers set " nak " in pid of corresponding pipe wait until pbusy bit of corresponding pipe goes to " 0 " or the controller detect to usb detach * start pipe information modification request pipe information modification * pbusy may not changed from " 1 " when detect usb detach during usb tranfer . figure 3 . 13 pipe information modification process from usb transmission enabled (pid=buf ? ) status in addition, the following pipe control register bits can only be re - written with pipe information that is not set in the curpipe bit of cpu/dma0/dm a1 - fifo ports. register cannot be set while corresponding pipe number is set in fifo port curpipe bits: (1) all bits of dcpcfg and dcpmaxp registers (2) all bits of pipecfg , pipebuf , pipemaxp and pipeperi registers (3) an aclrm bits of pipe xctr registers when modify ing information of a pipe, specify other pipe number in the curpipe bit. also, after setting the dcp pipe information, execute the clear process for the buffer using the bclr bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 94 of 142 jun 28,2013 3.3.4 data pid sequence bit when a normal data transfer occurs in the control tr ansfer data stage, bulk transfer or interrupt transfer, the controller automatically toggles the data pid sequence bit. the next data pid sequence bit for data transfer can be confirmed in the sqmon bit in the dcpctr or pipexctr registers. the sequence bit is switched in the ack handshake receive timing when data is sent or in the ack handshake send timing when data is received. the data pid sequence bit can also be modified for the sqclr and sqset bits of the dcpctr and pipexctr registers. for control tran sfers, the controller automatically sets the sequence bit for stage transitions. in control transfers, the controller automatically sets the sequence bit when the stage transitions. the bit goes to data 1 when the setup stage completes . the sequence bit doe sn't refer , and responds with data1 in the status stage. therefore, the bit does not need to be set with software. note : the data pid sequence bit must be set with software when a clearfeature request is received. finally, the sequence bit cannot be contro lled through the sqset bit for the isochronous transfer setup pipe.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 95 of 142 jun 28,2013 3.4 buffer memory this section describes operations concerning the controller ? s built - in buffer memory. 3.4.1 buffer memory allocation figure 3.14 prov ides an example buffer memory map of the controller. the buffer memory is an area shared by the cpu that controls the user system and this controller. the various buffer memory conditions determine access authority for the user system (cpu side) and/or thi s controller (sie side). the buffer memory is set into independent areas for each pipe. the memory area is set in 64 - byte blocks by the block start addresses and the number of blocks (set in pipebuf register bufnmb bit and bufsize bit). when selecting th e continuous transfer mode with the pipecfg register cntmd bit, make sure the bufsize bit is set in integral multiples of the maximum packet size. also, when selecting the double buffer in the pipecfg register dblb bit, 2 areas of the memory specified in t he pipebuf register bufsiz e bit will be allocated for the corresponding pipe. three fifo ports are used for access (data read/write) to the buffer memory. the pipe number of the pipe assigned to each fifo port is specified in the c/dxfifosel register curp ipe bit. the buffer status (enable/disable access for data read/write to buffer memory from cpu) of each pipe can be confirmed in the bsts and inbufm bits of the dcpctr and the pipexctr registers. also, fifo port access authorization can be confirmed in t he c/dxfifoctr register frdy bit.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 96 of 142 jun 28,2013 pipe assignment example 4 5 6 8 9 14 15 7 0 1 2 3 32 47 48 63 80 95 fifo port d0fifo port no setup register (bu fnmb=0, bufsize=3, dblb=0) fixed equivalently) cfifo port d1fifo port curpipe=3 buffer memory pipebuf reg set value pipe0 (dcp) pipe6 pipe7 pipe5 pipe1 pipe2 pipe3 pipe4 bufnmb=4, bufsize=0 bufnmb=5, bufsize=0 bufnmb=6, bufsize=0 bufnmb=8, bufsize=7 bufnmb=16, bufsize=7 bufnmb=32, bufsize=15 bufnmb=48, bufsize=15 curpipe=6 pipe8 pipe9 bufnmb (bufsize+1) x (dblb+1) bufnmb=7, bufsize=0 bufnmb=80, bufsize=15 curpipe=1 pipecfg reg dblb bit set value dblb=0 dblb=0 dblb=0 d blb=0 dblb=1 dblb=0 dblb=1 dblb=0 dblb=0 no. 16 22 23 96 137 unassigned fixed area (cannot be changed by software) 24 31 64 79 setting examples (can be changed by software) figure 3 . 14 buffer memory map example
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 97 of 142 jun 28,2013 3.4.1.1 buffer status table 3.10 shows the buffer statuses for the c ontroller. the buffer memory status can be confirmed with the bsts and inbufm bits. the direction of buffer memory access can be specified in the pipecfg register dir bit or the cfifosel register isel bit (in the dcp setting). the inbufm bit is only valid in the send direction of pipes 1 to 5. when the send - side transfer pipe is set to double buffer, the bsts bit is used to determine the status of the cpu - side buffer and the inbufm bit is used to determine the status of the sie - side buffer. if the write ev ent to the fifo port using the cpu (dm a c) is slow and the buffer empty space cannot be determined by the bemp interrupt, send completion can be confirmed with the inbufm bit. table 3 . 10 buffer status confirma tion with bsts bit isel or dir bsts buffer memory status 0 (receive direction) 0 no receive data or now receiving. fifo port is read - disabled. 0 (receive direction) 1 receive data is in fifo buffer or zero - length packet is received. fifo port is read -en abled. however, when zero - length packet is received the fifo port is read- disabled and the buffer must be cleared. 1 (send direction) 0 send is not completed. fifo port is write - disabled. 1 (send direction) 1 send is completed. fifo port is write - enable d. table 3 . 11 buffer status confirmation with inbufm bit dir inbufm buffer memory status 0 (receive direction) invalid invalid 1 (send direction) 0 send data transfer is complete. no send data in fifo buf fer 1 (send direction) 1 send data is written from fifo port. send data is in fifo buffer. 3.4.1.2 buffer clear table 3.12 shows the buffer memory clear conditions for the controller. the following 4 bits can clear the buffer memory. table 3 . 12 buffer clear bits bit name bclr dclrm aclrm register cfifoctr register dxfifoctr register dxfifosel register pipexctr register function clears the cpu - side buffer memory of the pipe assigned to the cfifo port or dxfifo port automatically clears the buffer memory after data is read from the specified pipe. convenient function when using dmac to read data. refer to 3.4.3.4 clears the sie - side buffer memory of the corresponding pipe by writing ?1 ? and ?0 ? consecutively to the aclrm bit. setup method clear the buffer memory by setting ? bclr=1 ?. (automatically returns to ? bclr=0 ? ) set ? dclrm=1 ? to enable mode. set ? dclrm=0 ? to disable mode. set ? aclrm=1 ? to e nable mode. set ? aclrm=0 ? to disable mode.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 98 of 142 jun 28,2013 3.4.1.3 buffer area table 3.13 shows the buffer memory map for the controller. the buffer memory consists of a fixed area in which pipes are pre - assigned and a user area in whic h the user can set blocks as needed. the dcp buffer is a fixed area used only for control read transfers and control write transfers. pipes 6 - 9 are pre - assigned to areas. when not using one of these pipes, the user can assign one of pipes 1 - 5 to the unused pipe area and utilize as a user area. be careful to set the pipe areas so that they do not overlap. in addition, set the buffer size so that it is larger or equal than the maximum packet size. table 3 . 13 buf fer memory map buffer memory number buffer size assignable pipe 0 ? 3 256 bytes (64 bytes x 4 blocks) dcp - only fixed area 4 64 bytes pipe 6 fixed area 5 64 bytes pipe 7 fixed area 6 64 bytes pipe 8 fixed area 7 64 bytes pipe 9 fixed area 8 ? 135 (0x 87) 8192 bytes (64 bytes x 128 blocks) pipe 1 - 5 3.4.1.4 buffer memory specifications (single/double setting) pipes 1 - 5 can be specified as single or double buffers with the pipexcfg register dblb bit. the double buffer is a function that assigns doulbe areas i n the specified memory with the pipebuf register bufsize bit for one pipe. figure 3.14 is a double buffer setting example of pipe1 and pipe3 as seen in the buffer memory map example.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 99 of 142 jun 28,2013 3.4.1.5 buffer memory operations (con tinuous transfer setting) the cntmd bit in either the dcpcfg or pipexcfg register can be used to select the continuous or non - continuous transfer mode. selection can be made for pipes 0 -5. the continuous transfer mode sends/receives multiple transactions c ontinuously. when the continuous transfer mode is selected, data can be transferred up to the buffer size assigned to each pipe, without interrupts to the cpu. in the continuous send mode, the write data is sent divided into maximum packet sizes. if the s end data that is less than the buffer size (short packets or packets in natural number multiples of the maxpacketsize that are less than the buffersize ), ? bval=1 ? must be set after the send data is written. in the continuous receive mode, the brdy interrup t is not generated until packets are received up to the buffer size, the transaction count is completed, or a short packet is received. figure 3.15 shows a status transition example of the controller ? s cntmd bit and buffer memory. figure 3 . 15 cntmd bit and buffer memory status transition example
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 100 of 142 jun 28,2013 3.4.2 fifo port function this section describes the fifo port functions. table 3.14 shows definitions of the fifo port function settings for the controller. when data write access is enabled and data is written up to buffer full state (in non - continuous transfer: maximum packet size), the port automatically goes t o the usb bus send enabled status. to enable data send of less than buffer full (in non - continuous transfer: less than number of maximum packet size), the port must be set to write complete in the c/dxfifoctr register bval bit (dma transfer: dend signal). to send a zero - length packet, the port must be set to write complete in the bval bit in addition to clearing the buffer with the bclr bit of the same register. when a read access is executed, if all the data is read, the port automatically goes to the new packet receive enable status. however, when a zero - length packet is received (dtln=0), the data cannot be read and the buffer must be cleared in the bclr bit of the same register. the receive data length is confirmed in the c/dxfifoctr register dtln bit. table 3 . 14 fifo port function settings register bit bit name function refernece notes c/dxfifosel rcnt selects dtln read mode rew buffer memory window (re - read, re - write) 2.8.4 3.4.2.2 dclrm automatically clears buffer memory after specified pipe received date is read 2.8.11 3.4.1.2 3.4.3.4 dxfifo only dreqe dreq signal assert 3.4.3 dxfifo only mbw fifo port access bit width 2.8.5 3.4.2.1 bigend fifo port endian control 2.8.6 isel fifo port access direction 2.8.7 3.4.2.1 dcp only curpipe selects current pipe 2.8.8 c/dxfifoctr bval buffer memory write end 2.8.16 bclr clears cpu - side buffer memor y 2.8.17 3.4.1.2 frdy monitors fifo port ready 2.8.18 dtln confirms received data length 2.8.19 external pin dend buffer memory w rite end 1.4 3.4.3.3 dma transfer only
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 101 of 142 jun 28,2013 3.4.2.1 fifo port selection table 3.15 shows the list of pipes that can be selected in each fifo port. the pipes to be accessed are selected with the c /dxfifosel register curpipe bit. after selecting the pipes, confirm that the curpipe value written was read correctly (if the previous pipe number is read out, this indicates the controller is still processing the pipe change), then confirm that ? frdy=1 ? a nd access the fifo port. the pipe switch procedure when the fifo port is accessed to figure 3.16 is shown. also, select the bus width for the fifo port access with the mbw bit. the buffer memory access direction is determined by the isel bit for dcp, and the pipexcf g register dir bit for all other pipes. table 3 . 15 fifo port access by pipe pipe access method usable ports dcp cpu access cfifo port register pipe 1 - 9 cpu access cfifo port register dxfifo port r egister dma access dxfifo port register c / dxfifosel register curpipe bit set to 0 c / dxfifosel register curpipe bit set to the pipe number for access read the curpipe bit and confirm to match the value of write data and registed data . start access to fifo port after confirm to frdy update to " 1 " pipe switch procedure when fifo port is accessed figure 3 . 16 pipe switch procedure when fifo port is accessed
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 102 of 142 jun 28,2013 3.4.2.2 rew bit the rew bit the c/dxfifosel register in allows the user to tem porarily stop the current pipe access, execute access of another pipe, then continue the current pipe access process again. 3.4.2.3 transaction counter (read direction) the transaction counter enables the controller to recognize transfer completion after the sp ecified number of transactions has completed in the data packet receive direction. the transaction counter is a function that operates in correspondence to pipes set in the receive direction. this function can be used for read events from any fifo port. t he transaction counter includes the trncnt register, which specifies the number of transactions, and the current counter that counts the number of internal transactions. when the current counter reaches the specified number of transactions, the buffer memo ry goes to the read - enabled status, even if it is not full. the trclr bit can be used to initialize the current counter in the transaction counter function so that the transaction can counted from the beginning again. also, the information read from the t rncnt register can be switched by setting the trenb bit accordingly. trenb=0: the set transaction counter value is read out trenb=1: the current counter value counted internally is read out modification conditions for the curpipe are as follows: (1) do not c hange the curpipe setting until the transaction in the specified pipe is completed. (2) the curpipe cannot be changed unless the current counter is cleared. trclr bit usage conditions are as follows. (1) the current counter cannot be cleared while a transaction i s in process and ? pid=buf ?. (2) the current counter cannot be cleared when data remains in the buffer.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 103 of 142 jun 28,2013 3.4.3 dma transfer (dxfifo port) 3.4.3.1 dma transfer outline pipes 1 - 9 can be used for fifo port access with dmac. when access becomes enabled for the pipe set by dma, the dreq signal is asserted. the dma transfer can be executed in the cycle steal transfer mode, which asserts the dreq signal every time one data (8 - bit or 16- bit) is transferred, or in the burst transfer mode, in which the dreq signal is continually ass erted until all data transfers in the buffer memory are completed. the timing is described in detail in ? chapter 4. electric characteristics. ? select the fifo port transfer unit (8 bits or 16 bits) with the dxfifosel register mbw bit and the dma transfer p ipe with the curpipe bit. note that the pipe (value set in curpipe bit) should not be changed during a dma transfer. 3.4.3.2 dma control signal selection select the pin for dma transfers in the dmaxcfg register dform bit and control the dreqx_n pin with the dxfif osel register dreqe bit. table 3.16 provides the list of dma control pins and figure 3.17 shows the fifo port access method and the dma control pin. table 3 . 16 dma control pin list access method register pin reference dreqe dform data bus dreq dack r d /wr addr +cs cpu bus 0 0 0 0 0 cpu - - cpu access cpu bus 1 1 0 0 0 cpu - dma through cpu bus cpu bus 2 1 0 1 0 cpu *1) dma through cpu bus cpu bus 3 1 0 1 1 cpu - *1) dma through cpu bus split bus 1 1 1 0 split - - split bus *1) when setting this access method, set the cs_n to inactive (fix to ?high?) while accessing the dxfifo port. dreq dack d15 - 0 cp u bus 1 dma transfer cpu bus 2 dma transfer dend dreq dack sd7 - 0 split bus dma transfer dend rd/wr cs addr figure 3 . 17 fifo port access and dma control pin
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 104 of 142 jun 28,2013 3.4.3.3 d end pint the controller can end a dma transfer using the dend pin. the dend pin also functions as input/output according to the usb data transfer direction. (1) buffer memory read direction the dend pin can perform as an output pin and notify the external dma controller of the last data transfer. the dend signal assert conditions can be set in the dmaxcfg register pktm bit. table 3.17 provides a list of dend pin asserts. table 3 . 17 dend pin assert list event pktm transaction count end brdy generated due to packet receive receive short packet other than zero - length receive zero - length packet when buffer is not empty receive zero - length packet when buffer is empty *2) 0 asser t no assert assert assert assert 1 assert assert assert assert no assert *1) the dreq signal is not asserted if a zero - length packet is received when the buffer is empty. (2) buffer memory write direction the dend pin becomes an input pin and the buffer memory goes to send - enabled (same status as when ? bval=1 ? ) when an active edge is detected. 3.4.3.4 dxfifo automatic clear mode (dxfifo port read direction) when a data read event of the controller buffer memory is completed with setting dxfifosel register dclrm bit to ?1 ? , the buffer memory of the corresponding pipe is automatically cleared. table 3.18 shows the correspondence between the packet received and the buffer memory clear process by software in each setting. as indicat ed in table 3.18 , the buffer clear conditions differ according to the bfre bit set value, even for statuses in which clear is normally required, using the dclrm bit eliminates the need for buffer clear by software, enabling dma transfers without the use of software. note that this function only has supports the buffer memory read direction setting. table 3 . 18 correspondence of packet receive and buffer memory clear proce ss by software register setting buffer state when packet received dclrm = 0 dclrm=1 bfre=0 bfre=1 bfre=0 bfre=1 buffer full clear unnecessary clear unnecessary clear unnecessary clear unnecessary zero - length packet received clear necessary clear neces sary clear unnecessary clear unnecessary normal short packet received clear unnecessary clear necessary clear unnecessary clear unnecessary transaction count end clear unnecessary clear necessary clear unnecessary clear unnecessary
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 105 of 142 jun 28,2013 3.4.3.5 brdy interrupt t iming selection function the pipecfg register bfre bit can be set so that the brdy interrupt is not generated when a data packet of maximum packet size is received. when using a dma transfer, this function enables an interrupt to be generated only when the last data is received. the last data indicates either a short packet receive or the transaction count end. by setting ? bfre=1 ? , the brdy interrupt will be generated after the received data is read. by reading the dnfifoctr register dtln bit, the receive d ata length of last data packet received just before the brdy interrupt was generated can be confirmed. table 3.19 shows the timing of the brdy interrupt. table 3 . 19 br dy interrupt generation timing list registration setting buffer state when packet received bfre = ?0? bfre = ?1? buffer full (normal packet received) when packet is received no interrupt generated zero - length packet received when packet is received when packet is received normal short packet received when packet is received when read event of data received from buffer memory is completed transaction count end when packet is received when read event of data received from buffer memory is completed the b fre bit function is only valid in the read direction of the buffer memory. when in the write direction, fix the bfre bit to ?0?.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 106 of 142 jun 28,2013 3.4.4 fifo port access enable timing this section describes the fifo port access enable timing. 3.4.4.1 fifo port access enable timing a t pipe switch figure 3.18 shows the timing diagram up to confirmation of the frdy and drln bits when the pipe specified by the fifo port is switched (modified c/dxfifosel register curpipe bit). when the curpipe bit is modified, first confirm that the written curpipe value was read correctly (if the previous pipe number is read out, this indicates the controller is still processing the pipe modification ), then confirm that ? frdy=1 ? and access the fifo port. the same timing applies to modification of the isel bit for the cfifo port. figure 3 . 18 frdy, drln fix timing after pipe switch 3.4.4.2 fifo port access enable timing after double buffer read/wri te is completed figure 3.19 shows the timing diagram up to when access is enabled for the second buffer, after the buffer read or write is completed in the double buffer mode. in the double buffer mode, always acces s the fifo port after waiting 300ns after the access just before the toggle. the same timing is applied to sending a short packet by setting ? bval=1 ? in the in direction pipe. figure 3 . 19 figure 3.18 frdy, dtln confirmation timing after double buffer read/write complete
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 107 of 142 jun 28,2013 3.5 data setup timing this section describes the obus bit that sets the split bus timing. the timing of the sd0 - 7 and dend pins can be modified through the dmaxcfg register obus bit as described in table 3.20 . the obus bit function is only valid for dma transfers using a split bus. when using the cpu bus for dma transfers, the obus bit setting is ignored. table 3 . 20 operation differences according to obus bit setup value direction obus bit setting operation read 0 sd0 - 7/dend signals are output normally, regardless of the control signal *1. if the control signal is negated, the next data is output. therefore, the dmac data setup timing is secured and hi - speed dma transfer is enabled. 1 sd0 - 7/dend signals are output after the control signal is asserted. sd0 - 7/dend signals go to hi - z if the control signal is negated. write 0 sd0 - 7/dend signals are output normally, regardless of the dackx_n signal. the dmac can output the next data before the dackx_n signal is asserted. therefore, the controller data setup timing is secured and hi - speed dma transfer is enabled. 1 sd0 - 7/dend sign als are input - enabled only when the dackx_n signal is asserted. sd0 - 7/dend signals are ignored if the dackx_n signal is negated. *1) the control signal indicates dackx_n when dmaxcfg register dform [9 ? 7] is ?100?. when ?obus=0? is set in the read direction , sd0 - 7/dend signal are always output. note that, therefore, when sharing the bus with another device, ?obus= 1 ? shall be set. when ?obus=0? is set in the write direction, sd0 - 7/dend signals are always input - enabled. do not allow the signals to be used as m id - rail voltage. figure 3.20 shows the configuration of data setup timing by the obus bit. obus=1: normal mode obus=0: high - speed mode dreq dack sd7 - 0 dend figure 3 . 20 data setup timing configuration
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 108 of 142 jun 28,2013 3.6 control transfer (dcp) data transfer in the data stage of the control transfer uses the default control pipe (dcp). the dcp buffer memory is a 256- byte single buffer fixed area used for both control read and control write events. only the cfifo port is en abled for access to the buffer memory. 3.6.1 setup stage the controller always responds with an ack when it receives a normal setup packet. the controller operations in the setup stage are as follows. (1) when a new setup packet is received, the controller sets th e following bits. (a) sets intsts0 register valid bit to ?1?. (b) sets dcpctr register pid bit to ?nak?. (c) sets dcpctr register ccpl bit to ?0?. (2) when a data packet is received following the setup packet, the usb request parameters are stored in the following registe rs: usbreq , usbval , usbindx and usbleng . always set ? valid=0 ? in the response process to a control transfer. in the ? valid=1 ? state, ? pid=buf ? will not be set and the data stage cannot be completed. the valid bit function allows the controller to temporar ily stop a request in - process when it receives a new usb request during a control transfer, and respond to the newest request. in addition, the controller automatically judges the direction bit (bmrequesttype bit 8) and the request data length (wlength) of the received usb request and determines whether it is a control read transfer, control write transfer or no- data control transfer , and then handles the stage transition. if the sequence is incorrect, a sequence error for the control transfer stage trans ition interrupt occurs and is notified to the software. for more information concerning the controller stage management, refer to figure 3.11 . 3.6.2 data stage use the dcp for data transfers in response to receiving a us b request. before accessing the dcp buffer memory, set the access direction in the cfifosel register isel bit. also set the transfer direction in the dcpcfg register dir bit. the transaction is executed by set ting the the pid bit of the dcpcfg register to buf. data transfer completion is detected by the brdy or bemp interrupts. use the brdy interrupt for control write transfers and the bemp interrupt for control read transfers. for control write transfers in hi - speed operation , a nyet handshake is sent in a ccordance with the buffer memory status. for more details, see chapter 3.7.1 , 3.6.3 status stage when the dcpctr register pid bit status is ? pid=buf ? , set the ccpl bit to ? 1 ? to complete the control transfer. after the above settings, the controller automatica lly executes the status stage in accordance with the data transfer direction fixed in the setup stage. the detailed process is as follows. (1) control read transfers: the controller sends a zero - length packet and receives an ack response from the usb host cont roller. (2) control write transfers and no- data control transfers: the controller receives a zero - length packet from the usb host and sends an ack response.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 109 of 142 jun 28,2013 3.6.4 control transfer automatic response function the controller automatically sends a response to a norm al set address request. if one of the following errors occurs , a response must be sent by software. (1) bmrequesttype ? 0x00? (2) windex ? 0x00? (3) wlength ? 0x00? (4) wvalue > ? 0x7f ? (5) wvalue 0 and dvsq = "011" (6) wvalue = 0 and dvsq = "001" all requests other than the set address request must be responded to by software.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 110 of 142 jun 28,2013 3.7 bulk transfer (pipes 1 - 5) the user can select the buffer memory usage method (single/double buffer, continuous/non - continuous transfer mode) for the bulk transfer mode . the buffer memory size can be set up to a 2k - byte double buffer. the controller manages the buffer memory state and automatically respon ds to ping packets and nyet handshakes. 3.7.1 nyet handshake control table 3.21 shows the list of responses to a token received in a bulk or control transfer. when an out token is received in a bulk or control transfer and there is only enough open space for one packet in the buffer memory, the controller sends a nyet response. however, when a short packet is received, the controller sends an ack response instead of a nyet response, even under these conditions. table 3 . 21 response list for received tokens pid bit set value buffer memory status *1) receive token response notes nak /stall - setup ack - - in/out /ping nak /stall - buf - setup ack - rcv - brdy out /ping ack receive data packet at out token receive *1 rcv - brdy out nyet receive data packet *2 rcv - brdy out (short) ack receive data packet *2 rcv - brdy ping ack *2 rcv - nrdy out / ping nak trn - brdy in data0 / 1 send data packet trn - n rdy in nak *1) further response details: rcv - brdy*1: buffer memory has enough space for 2 packets or more when out/ping token is received. rcv - brdy*2: buffer memory has only enough space for one packet when out token is received rcv - nrdy: buffer memory has n ot enough space for one packet when ping token is received. trn - brdy: buffer memory has send data when in token is received. trn - nrdy: buffer memory does not have send data when in token is received. 3.8 interrupt transfer (pipes 6 - 9) t he controller executes an interrupt transfer in accordance with the period managed by the host controller. the controller ignores (no response) ping packets in interrupt transfers. in addition, the controller does not send a nyet handshake, but responds with ack, nak or stall. the r8a6659 3 controller does not support high - bandwidth transfers in the interrupt transfer mode.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 111 of 142 jun 28,2013 3.9 isochronous transfer (pipes 1 - 2) the controller provides the following functions for isochronous transfers. (1) isochronous transfer error information notificat ion (2) interval counter ( iitv bit setting) (3) isochronous in transfer data setup control ( idly function) (4) isochronous in transfer buffer flush function ( ifis bit setting) (5) sof pulse output function the controller does not support high - bandwidth isochronous transf ers.. 3.9.1 isochronous transfer error detection the controller manages isochronous transfer errors by software and therefore has the following error information detection functions. table 3.22 and table 3.23 describe the procedure in which errors are confirmed and the interrupts that are generated . (1) pid error when the receive packet pid is corrupted (2) crc error and bit stuffing error when an error occurs in the receive packet crc o r when the bit stuffing is corrupted . (3) maximum packet size over this indicates the data size of the receive packet is larger than the value set for the maximum packet size. (4) overrun and underrun (a) when there is no data in the buffer memory at an in token recei ve for an in - direction (send) transfer (b) when there is no empty space in the buffer memory at an out token receive for an out - direction (receive) transfer (5) i nterval error (a) when an in token could not be received in the interval frame of an isochronous in transf er (b) when an out token could not be received in the interval frame of an isochronous out transfer table 3 . 22 errors detected at token receive/send priority of detected errors error type generated interrupts and status at time of error detection 1 pid error no interrupt generated (ignored as corrupted packet) 2 crc error, bit stuffing error no interrupt generated (ignored as corrupted packet) 3 overrun, underrun nrdy interrupt is generated, and ovrn bit is set . a zero - length packet is sent in response to an in token. a data packet is not received in response to an out token. 4 interval error nrdy interrupt is generated. table 3 . 23 errors detected at data packet receive priority of detected errors error type generated interrupts and status 1 pid error no interrupt generated (ignored as corrupted packet) 2 crc error, bit stuffing error nrdy interrupt is generated, and crce bit is set. 3 maximum packet size ove r error bemp interrupt is generated, and pid is set to ? stall ? .
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 112 of 142 jun 28,2013 3.9.2 data - pid the r8a6659 3 controller does not support high - bandwidth transfers. t he following occurs in response to a received pid. (1) in direction (a) data0: sent as data packet pid (b) data1: not se nt (c) data2: not sent (d) mdata: not sent (2) out direction (in full - speed operation) (a) data0: received successfully as data packet pid (b) data1: received successfully as data packet pid (c) data2: ignored packet (d) mdata: ignored packet (3) out direction (in hi - speed operation) (a) dat a0: received successfully as data packet pid (b) data1: received successfully as data packet pid (c) data2: received successfully as data packet pid (d) mdata: received successfully as data packet pid 3.9.3 interval counter 3.9.3.1 operation outline the isochronous transfer interv al can be set in the pipeperi register iitv bit. table 3.24 shows the functions of the interval counter. table 3 . 24 interval counter functions transfer direction func tion detection conditions in send buffer flush function cannot successfully receive in token in interval frame in isochronous in transfer out token un - received notification cannot successfully receive out token in interval frame in isochronous out transf er the interval count is executed for an sof receive or a interpolated sof. therefore, when an sof is damaged, the isochrony can still be maintained. frame intervals are set as 2 iitv (u) frames. 3.9.3.2 interval counter initialization the controller initializes the interval counter under the following conditions. (1) h/w reset initializes the iitv bit. (2) buffer memory clear by aclrm bit this initializes the count but not the iitv bit. (3) usb bus reset after the interval counter is initialized and a packet is successfull y transferred, the interval count starts under the following conditions. (1) sof is received after data is sent in response to an in token in the ? pid=buf ? status (2) sof is received after data is received in response to an out token in the ? pid=buf ? status note that the interval counter is not initialized in the following conditions. (1) when the pid is set to nak or stall the interval timer is not stopped at this time. the transaction will be attempted at the next interval. (2) usb bus reset or usb suspend the iitv bit is not initialized at this time. when the sof is received, the count starts from the value before the
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 113 of 142 jun 28,2013 receive. 3.9.4 isochronous transfer send data setup a fter data is written to the buffer memory in the isochronous transmission, the data packet can be sent out in the next frame detected after the sof packet. this function, called the isochronous transfer send data setup function, allows the frame that started the send to be specified. when using the buffer memory as a double buffer and both buffers have been wri tten, only the first buffer memory to complete the write event is transfer - enabled. therefore, even when several in tokens are received in the same frame, only one packet of data is sent by the buffer memory. when an in token is received, if the buffer me mory is in the send - enabled state, the data transfer will be sent and a normal response returned. however, if the buffer memory is not in the send - enabled state, a zero- length packet is sent and an underrun error occurs. figure 3.21 shows a controller send example using the isochronous transfer send data setup function when ? iitv=0 (per frame) ? is set. transfer - enabled status writing buffer a buffer b write end writing write end empty state empty state in transfer - enabled writing buffer a buffer b write end writing write end empty state empty state in data - a writing write end empty state transfer - enabled status empty state in data - b in transfer - enabled writing buffer a buffer b write end writing write end empty state empty state in data - a writing write end empty state empty state in data - b in transfer - enabled status writing write end empty state in in empty state in buffer a buff er b empty state data - a receive token send packet receive token send packet receive token send packet receive token zero - length zero - length zero - length zero - length sof sof sof sof sof sof sof sof sof sof sof sof sof (1) receive start example 1 (when send data is ready before in token receive start) send packet (2) receive start example 2 (ex. 1 of when send data is ready after in token receive start) (3) receive start example 2 (ex. 2 of when send data is ready after in token receive start) (3) example of irregular period in token receive zero - length transfer - enabled status figure 3 . 21 data setup function operati on
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 114 of 142 jun 28,2013 3.9.5 isochronous transfer send buffer flush i f the controller does not receive an in token in the interval frame in the isochronous data send but receives the ( ) sof packet in the next frame, the in token is handled as a corrupted token and the buffer tha t is send - enabled is cleared set to the write - enabled status. at this time, if the double - buffer is used and the write event to both buffers is complete, the cleared buffer memory is assumed to be sent in the interval frame, and the other side buffer memor y is set to the transfer - enabled status at the received the next (u) sof packet. the operation start timing of the buffer flush function differs according to the value set in the iitv bit, as follows. (1) when iitv=0 the buffer flush operation is executed from the first frame after the pipe becomes valid. (2) when iitv > 0 the buffer flush operation is executed after the first successful transaction. figure 3 . 22 provides an operation example of the controller buffer flush function. when a token is received outside of the specified interval period (before the interval frame), a written data packet or a zero - length packet is sent as an underrun error according to the data setup status sof sof sof sof transfer - enabled writing buffer a buffer b write end writing write end empty s empty s empty s writing write end transfer - e nabled status buffer flush generated figure 3 . 22 buffer flush function operation example figure 3.23 shows an example of an interval error generated in the controller. there are 5 types of interval errors, as listed below. timing 1 in the figure shows when the interval error occurs and how the buffer flush function operates. when an interval error occurs during an in transfer , the buffer flush function goes into operation; during an out transfer, the nrdy interrupt is generated. use the ovrn bit to determine whether an error is an nrdy interrupt, such as a receive packet error, or an overrun error. responses to the tokens in the shaded boxes are executed in accordance to the buffer memory status. (1) in direction: (a) if buffer is in transf er - enabled status, data is transferred a s a normal response (b) if buffer is in transfer - disabled status, zero - length packet is sent and underrun error occurs (2) out direction: (a) if buffer is in receive - enabled status, data is received a s a normal response (b) if buff er is in receive - disabled status, data is not received and overrun error occurs token (1) successful transfer token token token (2) damaged to ken token token token token (6) delayed token token token token token (4) frame miss (1) token token token (3) packet insertion token token token token (5) frame miss (2) token token token token 1 1 1 1 1 1 1 sof token token t oken received according to interval token received in frame outside of interval interval when iitv=1
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 115 of 142 jun 28,2013 figure 3 . 23 interval error occurrence example when "iitv=1" 3.10 sof interpolation function when a receiv e is unsuccessful in the 1ms (full - speed operation) or 125us (hi - speed operation) interval due to sof packet damage or loss, the sof is interpolated by the controller internally. the start condition of the sof interpolation is "usbe=1", "scke=1" and sof pa cket receive. the controller initializes the sof interpolation function under the following conditions. (1) h/w reset (2) usb bus reset (3) suspend detection the sof interpolation operates according to the following specifications. (1) frame interval (125 us or 1ms) is b ased on the results of the reset handshake protocol. (2) the interpolation function does not operate until the sof packet is received. (3) after the first sof packet is received, the internal clock counts 125us or 1ms at 48mhz, then interpolates. (4) interpolation is performed in the previous receive intervals after the 2nd and later sof packets are received. (5) interpolation is not performed in the suspend state or during a usb bus reset receive. when the controller goes to the suspend state in hi - speed operation, interp olation continues after 3ms from the last packet. the sof interpolation function runs in the following functions. (1) frame number or micro - frame number update (2) sofr interrupt, sof lock (3) sof pulse output (4) isochronous transfer inter val count when an sof packet is lost during full - speed operation, the frmnum register frnm bit is not updated. when a sof packet is lost during hi - speed operation, the ufrmnum register ufrnm bit is updated. however, when a ? frnm=000 ? sof packet is lost, the frnm bit is not updated. at this time, even if sof packets other than the ? frnm=000 ? packet are received successfully, the frnm bit is not updated. 3.10.1 sof pulse output when sof output is enabled, the controller outputs the sof pulse according to the sof timing. when the value of the sofcfg register osfm bit is ? 01? (1ms sof) or ?10? (125 s sof), the pulse is output in the ?l ? active state from the sof n pin. this is called the ? sof signal ? . for more details concerning the pulse timing, refer to f igure 3.24 . sof packet receive or sof output due to ? sof interpolation ? are output at even intervals. usb bus sof packet 1ms(full-speed) / 125us(high-speed) sof minimun 640ns sync pid frame crc5 figure 3 . 24 sof output timing
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 116 of 142 jun 28,2013 3.11 usb connector connection example figure 3.25 shows an example of the connection between the controller and usb connector . r8a 6659 3 vbus usb connector 1 3 2 4 gnd d - d + vbus d m0 d p0 d+ and d - lines must be configured to support impedance control ref r in 5.6k ohm agnd figure 3 . 25 usb connector connection example
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 117 of 142 jun 28,2013 4 electri cal c haracteristics 4.1 absolute m aximum r atings symbol item rated vlalue unit vif io power supply voltage - 0.3 ~ +4.0 v vcc power supply voltage (3.3v) - 0.3 ~ +4.0 v avcc analog power supply voltage (3.3v) - 0.3 ~ +4.0 v vbus vbus input voltage - 0.3 ~ +5.5 v v i (io) system interface input voltage - 0.3 ~ vif+0.3, vcc+0.3 v v o (io) system interface output voltage - 0.3 ~ vif+0.3, vcc+0.3 v pd power consumption 600 mw ts t g storage temperature - 55 ~ +150 degrees celcius 4.2 recommended o perating c onditions symbol item rated value unit min imum average maximum vif io power supply voltage 1.8v supported 1.6 1.8 2.0 v 3.3v supported 2.7 3.3 3.6 v vcc p ower supply voltage (3.3v) 3.0 3.3 3.6 v avcc analog power supply voltage (3.3v) 3.0 3.3 3.6 v agnd analog power supply gnd 0 v gnd power supply gnd 0 v v i (io) system interfaceinput voltage 0 vif, vcc v v i (vbus) i nput voltage (vbus input only) 0 5.25 v v o (io) system interface output voltage 0 vif, vcc v topr ambient operating temperatrure r8a6659 3 fp (standard items ) -20 +25 +85 degrees celcius tr, tf input rise, fall times normal input 500 ns schmitt t rigger input 5 ms
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 118 of 142 jun 28,2013 4.3 electrical c haracteristics (ratings for vif = 2.7~3.6v) symbol item measurement conditions rated value unit min imum typ ical maximum v ih "h" input voltage note 1 vcc = 3.6v 2.52 3.6 v v il "l" input voltage vcc = 3.0v 0 0.9 v v ih "h" input voltage note 2 vif = 3.6v 0.7vif 3.6 v v il "l" input voltage vif = 2.7v 0 0.3vif v vt+ threshold voltage in positive directio n note 3 vif = 3.3v 1.4 2.4 v vt - threshold voltage in negative direction 0.5 1.65 v vth hysteresis voltage 0.8 v v oh "h" output voltage xout vcc = 3.0v i oh = - 50ua 2.6 v v ol "l" output voltage i ol = 50ua 0.4 v v oh "h" output voltage not e 4 vif = 2.7v i oh = - 4ma vif - 0.4 v v ol "l" output voltage i ol = 4ma 0.4 v v oh "h" output voltage note 5 vif = 2.7v i oh = - 2ma vif - 0.4 v v ol "l" output voltage i ol = 2ma 0.4 v vt+ threshold voltage in positive direction vbus vcc = 3.3v 1.4 2.4 v vt - threshold voltage in negative direction 0.5 1.65 v i ih "h" input current vif,vcc = 3.6v v i = vif,vcc 10 ua i il "l" input current v i = gnd - 10 ua i ozh "h" output current in off stauts note 6 vif = 3.6v v o = vif 10 ua i ozl "l" out put current in off stauts v o = gnd -10 ua rdv pull - down resistance vbus 500 k icc(a) average supply current during h s operation note 7 f(x in ) = 48mhz vif, vcc, avcc = 3.6v 50 ma icc(a) average supply current during fs operation note 7 f(x in ) = 48mhz vif, vcc, avcc = 3.6v 22 ma icc(s) supply current in static mode note 7 us b suspend status vif = 3.6v 0.35 ma usb cable detached vif = 3.6v 0.15 ma vcc,avcc=0v,vif=3 . 6 v under 0.01 ma c in pin capacitance (input) 7 pf c out pin capacitance (output / i/o) 7 pf note 1: x in , note 2: mpbus, a7 -1 , input pin and dend0 - 1_n, sd7 - 0, d15 - 0 input/output pin note 3: dack0 - 1_n, rst_n, rd_n, wr0 - 1_n, cs_n input pin note 4 : dreq0 - 1_n output pin, and dend0- 1_n, sd7 - 0, d15 - 0 input/output pin note 5 : int_n,sof_n output pin note 6 : dend0 - 1_n, sd7 - 0, d15- 0 input/output pin s note 7 : supply current is the total of vif, vcc, and avcc currents
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 119 of 142 jun 28,2013 4.4 electrical c haracteristics ( r atings for vif = 1. 6 ~ 2.0v) symbol item measurement conditions rated value unit min imum typical maximum v ih "h" input voltage note 1 vcc = 3.6v 2.52 3.6 v v il "l" input voltage vcc = 3.0v 0 0.9 v v ih "h" input voltage note 2 vif = 2.0v 0.7vif 3.6 v v il "l" input voltage vif = 1.6v 0 0.3vif v vt+ threshold voltage in positive direction note 3 vif = 1.8v 0.7 1.4 v vt - threshold voltage in nega tive direction 0.2 0.8 v vth hysteresis voltage 0.5 v v oh "h" output voltage xout vcc = 3.0v i oh = - 50ua 2.6 v v ol "l" output voltage i ol = 50ua 0.4 v v oh "h" output voltage note 4 vif = 1.6v i oh = - 4ma vif - 0.4 v v ol "l" output voltage i ol = 4ma 0.4 v v oh "h" output voltage note 5 vif = 1.6v i oh = - 2ma vif - 0.4 v v ol "l" output voltage i ol = 2ma 0.4 v vt+ threshold voltage in positive direction vbus vcc = 3.3v 1.4 2.4 v vt - threshold voltage in negative direction 0.5 1.6 5 v i ih "h" input current vif = 2.0v vcc = 3.6v v i = vif,vcc 10 ua i il "l" input current v i = gnd - 10 ua i ozh "h" output current in off stauts note 6 vif = 2.0v v o = vif 10 ua i ozl "l" output current in off stauts v o = gnd -10 ua rdv pull - down resistance vbus 500 k icc(a) a verage supply current during h s operation note 7 f(x in ) = 48mhz vif=2.0v, vcc, avcc = 3.6v 50 ma icc(a) average supply current during fs operations note 7 f(x in ) = 48mhz vif=2.0v,vcc,avcc = 3.6v 20 ma icc(s) supply current in static mode note 7 usb suspend status vif = 2.0v 0. 3 5 ma usb cable detached status vif = 2.0v 0.15 ma vcc,avcc=0v,vif 2.0 v undewr 0.01 ma c in pin capacitance ( i nput) 7 pf c out pin capacitance (output / i/o) 7 pf note 1: x in , note 2: mpbus, a7 -1 , input pin, and dend0 - 1_n, sd7 - 0, d15 - 0 input/output pins note 3: dack0 - 1_n, rst_n, rd_n, wr0 - 1_n, cs_n input pins note 4 : dreq0 - 1_n output pin, and dend0 - 1_n, sd7 - 0, d15 - 0 input/output pin note 5 : int_n,sof_n output pin note 6 : dend0 - 1_n, sd7 - 0, d15-0 input/output pins note 7 : supply current is the total of vif, vcc, and avcc currents
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 120 of 142 jun 28,2013 4.5 measurement c ircuit 4.5.1 pins except usb buffer section c l r l = 1 k ? sw 2 sw 1 c l elements to be measured p . g . r l = 1 k ? vif , vcc vif , vcc input tdis ( ctrl ( lz )) tdis ( ctrl ( hz )) ta ( ctrl ( zl )) ta ( ctrl ( zh )) item sw 1 sw 2 closed closed open open open closed closed open ( 1 ) input pulse level : 0 - 3 . 3 v , 0 - 1 . 8 v input pulse rise / fall time : tr , tf = 3 ns input timing standard voltage : vif / 2 , vcc / 2 output timing judge voltage : vif / 2 , vcc / 2 ( the tdis ( lz ) is judged by 10 % of the output amplitude and the tdis ( hz ) by 90 % of the output amplitude .) ( 2 ) the electrostatic capacity cl includes the stray capacitance of the wire connection and the input capacitance of the probe . 50 ? gnd d 15 - 0 , sd 7 - 0 , dend 0 _ n , dend 1 _ n other output 4.5.2 usb buffer block (full - speed ) c l d+ r l =15k ? c l d- r l =15k ? vcc gnd elements to be measured (1) the tr and tf are judged by the transition time of the 10% amplitude point and 90% amplitude point respectively. (2) the electrostatic capacity cl includes the stray capacitance of the wire connection and the input capacitance of the probe. dm dp 4.5.3 usb buffer block (hi - speed) c l d+ r l =45 ? c l d- r l =45 ? vcc gnd elements to be measured (1) the tr and tf are judged by the transition time of the 10% amplitude point and 90% amplitude point respectively (2) the electrostatic capacity cl includes the stray capacitance of the wire connection and the input capacitance of the probe. dm dp
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 121 of 142 jun 28,2013 4.6 electrical c haracteristics (d+/d - ) 4.6.1 dc characteristics symbol item measurement conditions rated value unit min imum typical max imum r ref reference resistance 5.544 5.6 5.656 k r o fs driver output impedance hs operation 40.5 45 49.5 fs operation 28 36 44 r pu d+, d - pull - up resistance idle status 0.9 1.575 k transmitting and receiving status 1.425 3.09 k input characteristics for full - speed operation v ih "h" input voltage 2.0 v v il "l" input voltage 0.8 v v di differential input sensitivity (d+) - (d - ) 0.2 v v cm differential common mode range 0.8 2.5 v output characteristics for full - speed operations v ol "l" output voltage vcc = 3.0v rl of 1 .5k to 3.6v 0.3 v v oh "h" output voltage rl of 15k to gnd 2.8 3.6 v v se single - ended receiver threshold voltage 0.8 2.0 v v ors output signal crossover voltage 1.3 2.0 v input characteristics for hi - speed operations v hssq s quelch detection th reshold voltage ( d ifferential) 100 150 mv v hscm common mode voltage range - 50 500 mv output characteristics for hi - speed operations v hsoi idle status - 10.0 10 mv v hsoh "h" output voltage 360 440 mv v hsol "l" output voltage - 10.0 10 mv v chir pj chirp ? j output voltage (differential) 700 1100 mv v chirpk chirp ? k output voltage (differential) -900 -500 mv ac characteristics (full - speed) symbo l item measurement conditions rated value unit min imum typical maximum tr rise transition time 10%90% of the data signal amplitude cl=50pf 4 20 ns tf fall transition time 90%10% of the data signal amplitude cl=50pf 4 20 ns trfm rise/ f all time matching t r/ t f 90 111.11 %
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 122 of 142 jun 28,2013 4.7 power s equence , reset timming 4.7.1 power sequence rst_n cs_n, wr0_n, wr1_n vcc min. 3 00 s min.500ns 3.0v 0.3v min. 0ns note: simultaneous power - on and power - off is recommended for vcc and avcc. vif power - on timing is recommended to be simultaneous with vcc and avcc, or to be earlier than vcc and avcc. the vif power - off timing is recommended to be simultaneous with vcc and avcc, or to be later than vcc and avcc. reset with rst_n is a must. if this sequence can't keep, normal operating is not guaranteed that even with conduct the operation of reset timing of the chapter 4.7.2. 4.7.2 reset timing of vcc=on status rst_n cs_n, wr0_n, wr1_n min. 1 00 n s min.500ns
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 123 of 142 jun 28,2013 4.8 switching c haracteristic (vif = 2.7~3.6v, or 1.6~2.0v) symbol item measurement conditions, etc. rated value unit reference number min imum typical maximum ta (a) address access time cl=50pf 30 ns 1 tv (a) time that data is val id after address cl=10pf 2 ns 2 ta (ctrl - d) time that data can be accessed after control cl=50pf 30 ns 3 tv (ctrl - d) time that data is valid after control cl=10pf 2 ns 4 ten (ctrl - d) time that data output is enabled after control 2 ns 5 tdis (ctrl - d) time that data output is disabled after control cl=50pf 30 ns 6 ta (ctrl - dv) time that data can be accessed after control when split bus (dma interface) obus=0 cl=30pf 30 ns 9 tv (ctrl ? dv) time that data can is valid after control when split bus (dma interface) obus=0 cl=10pf 2 ns 10 ta (ctrl - dendv) time that dend output can be accessed after control when split bus (dma interface) obus=0 cl=30pf 30 ns 11 tv (ctrl - dendv) time that dend output is valid after control when cp u bus and split bus (dma interface) obus=0 cl=10pf 2 ns 12 ta (ctrl - dend) time that dend output can be accessed after control when split bus (dma interface) obus=1 cl=30pf 30 ns 13 tv (ctrl ? dend) time that dend output is valid after control when cpu bus and split bus (dma interface) obus=1 cl=10pf 2 ns 14 ten (ctrl ? dend) time that dend output is enabled after control when cpu bus and split bus (dma interface) obus=1 2 ns 15 tdis (ctrl - dend) time that dend output is disabled after control when cpu bus and split bus (dma interface) obus=1 cl=30pf 30 ns 16 tdis (ctrl ? dreq) time that dreq is disabled after control 30 ns 17 tdis (ctrlh ? dreq) time that dreq is disabled after writing in dend input is completed and control is completed 30 ns 18 ten (ctrl ? dreq) time that dreq is enabled after control 20 70 ns 19 twh (dreq) dreq output "h" pulse width 20 50 ns 20 td (ctrl - int) int output negated delay time 250 ns 21 twh (int) int output "h" pulse width 650 ns 22 td (dr eq - dv) data access after dreq begins to be asserted when split bus (dma interface) obus=0 0 ns 23 td (dreq - dendv) dend output determination time after starting dreq assert, when split bus (dma interface) obus=0 or cpu bus1, 2 0 ns 24 tdis (pctr lh - dreq) time that dreq is disabled after end of previous control 70 ns 25 key : ta: access time, tv: valid time, ten: output enabled time, tdis: output disabled time , (a): address, (d): data, (dend): diend_n, (dreq): direq_n, (ctrl): control, (v): obus=0
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 124 of 142 jun 28,2013 4.9 required t iming c onditions (vif = 2.7~3.6v, or 1.6~2.0v) symbol item measurement conditions , etc. rated value unit ref erence number min imum typical maximum tsuw (a) address write s etup time cl=50pf 10 ns 30 tsur (a) address read s etup tim e 0 ns 31 tsu (a - ale) address s etup time when using multiplex bus 10 ns 32 thw (a) address write hold time 0 ns 33 thr (a) address read hold time 10 ns 34 th (a - ale) address s etup hold time when using multiplex bus 0 ns 35 tw (ale) ale pulse width when using multiplex bus 10 ns 36 tdwr (ale - ctrl) write/ r ead delay time when using multiplex bus 7 ns 37 trec (ale) ale recovery time when using multiplex bus 0 ns 38 tw (ctrl) control pulse width (write) 30 ns 39 trec (ct rl) control recovery time when using dma interface cycle steal 30 ns 40 (fifo) other than above mentioned 12 ns trecr (ctrl) control recovery time (reg) 12 ns 41 twr (ctrl) control pulse width (r ead) 30 ns 42 tsu (d) data s etup time 10 ns 43 th (d) data hold time 0 ns 44 tsu (dend) dend input s etup time 10 ns 45 th (dend) dend input hold time 0 ns 46 tw (cycle1) fifo/register access cycle time 8/16 - bit fifo access (separate bus) (other than cases corresponding to 47 - 2) 60 ns 47-1 8/16 - bit fifo access (multiplex bus) 84 ns tw (cycle2) fifo access cycle time only when dma interface dacki_n is used 8 - bit fifo access 30 ns 47-2 16- bit fifo access 50 ns tw (ctrl_b) control pulse width when using burst transf ers when using split bus and obus=0 12 ns 48 when using split bus and obus=1 (see note) 30 ns when using dma transfers with cpu bus 30 ns trec (ctrl_b) control recovery time for burst transfers 12 ns 49 tsud (a) dma address write s et up time 10 ns 50 thd (a) dma address write hold time 0 ns 51 tw (rst) reset pulse width time 100 ns 52
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 125 of 142 jun 28,2013 tst (rst) control starts width time after reset 500 ns 53 key tsuw: write s etup time, tsur: read s etup time, tsu: s etup time thw: write hold time, thr: read hold time, th: hold time, tw: pulse width, twr: read pulse width tdwr: read/ w rite delay time, trec: recovery time, trecr: register recovery time tsud: dma s etup time, thd: dma hold time, tst: start time (a): address, (d): data, (ctr l): control, (ctrl_b): burst control, (ale): ale
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 126 of 142 jun 28,2013 4.10 timing d iagrams 4.10.1 index for register access timing diagram bus s pecifications access r/w i ndex note separate bus cpu write 4.11.1.1 cpu bus 0 separate bus cpu r ead 4.11.1.2 cpu bus 0 multiplex bus cpu write 4.11.2.1 cpu bus 0 multiplex bus cpu read 4.11.2.2 cpu bus 0 4.10.2 index for fifo port access timing access bus i/f s pecifications i/f s pecifications w hen o perating dform b it set v alue obus b it set v alue r/w note i ndex cpu cpu bus 0 separate bus - w rite - cpu cpu bus 0 separate bus - r ead - 4.11.1.2 cpu cpu bus 0 multiplex bus - w rite - 4.11.2.1 cpu cpu bus 0 multiplex bus - r ead - 4.11.2.2 dma cpu bus 2 acknowledgement + rd/wr 010 w rite c ycle steal transfer 4.11.3.1 *1 dma cpu bus 2 acknowledgement + rd/wr 010 r ead cycle steal transfer 4.11.3.2 *1 dma cpu bus 1 separate bus 000 w rite cycle steal t ransfer 4.11.3.3 dma cpu bus 1 separate bus 000 r ead cycle steal transfer 4.11.3.4 dma split bus 2 acknowledgement only 100 1 w rite cycle steal transfer 4.11.3.5 *1 dma split bus 2 acknowledgement only 100 1 r ead cycle steal transfer 4.11.3.6 *1 dma split bus 2 acknowledgement only 100 0 w rite cycle steal transfer 4.11.3.5 *1 dma split bus 2 acknowledgement only 100 0 r ead cycle steal transfer 4.11.3.7 *1 dma cpu bus 3 acknowledgement only 011 w rite cycle steal transfer 4.11.3.8 *1 dma cpu bus 3 acknowledgement only 011 r ead cycle steal transfer 4.11.3.9 *1 dma cpu bus 1 multiplex bus 000 w rite cycle steal transfer 4.11.4.1 dma cpu bus 1 multiplex bus 000 r ead cycle steal transfer 4.11.4.2 dma cpu bus 2 acknowledgement + rd/wr 010 w rite burst transfer 4.11.5.1 *1 dma cpu bus 2 acknowledgement + rd/wr 010 r ead burst transfer 4.11.5.2 *1 dma cpu bus 1 separate bus 000 w rite burst transfer 4.11.5.3 dma cpu bus 1 separat e bus 000 r ead burst transfer 4.11.5.4 dma split bus 2 acknowledgement only 100 1 w rite burst transfer 4.11.5.5 *1 dma split bus 2 acknowledgement only 100 1 r ead burst transfer 4.11.5.6 *1 dma split bus 2 acknowledgement only 100 1 w rite burst transfer 4.11.5.5 *1 dma split bus 2 acknowledgement only 100 1 r ead burst transfe r 4.11.5.6 *1 dma split bus 2 acknowledgement only 100 0 w rite burst transfer 4.11.5.5 *1 dma split bus 2 acknowledgement only 100 0 r ead burst transfer 4.11.5.7 *1 dma cpu bus 3 acknowledgement only 011 w rite burst transfer 4.11.5.8 *1 dma cpu bus 3 acknowledgement only 011 r ead burst transfer 4.11.5.9 *1 dma cpu bus 1 multiplex bus 000 w rite burst transfer 4.11.6.1 dma cpu bus 1 multiplex bus 000 r ead burst transfer 4.11.6.2 note: *1) b ecause the address signal is not used, the timing will be the same for the separate bus and multiplex bus. ? the reading and writing timing are carried out using a control signal. if the control signal is configured from a combination of multiple signals, the rating from the falling edge will be valid starting from when the active delay signal changes. the ratings from the rising edge will be valid starting from the change in signals that become inactive more quickly.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 127 of 142 jun 28,2013 4.11 timing d iagram 4.11.1 cpu access timing (when a s eparate bus is set) 4.11.1.1 cpu access w rite timing (when a s eparate bus is set) 30 tsuw(a) thw(a) 33 tw(cycle1) tw(ctrl) trecr(ctrl) 47 -1 39 tsu(d) th(d) 43 44 a6-a1 cs_n d15-d0 note 1- 1 address determination 41 data determination note 1- 3 wr1_n, wr0_n trec(ctrl), 40 4.11.1.2 cpu access read timing (when a separate bus is set) 31 tsur(a) thr(a) tw(cycle1) twr(ctrl) trecr(ctrl) 47 -1 42 tv(ctrl-d) tdis(ctrl-d) 5 ten(ctrl-d) 6 41 ta(ctrl-d) 3 ta(a) 1 cs_n d15-d0 note 1- 2 2 34 tv(a) 4 note 1- 3 address determination data determination rd_n trec(ctrl), 40 a6-a1 note 1 - 1: the control signal when writing data is a combination of cs_n, wr1_n, and wr0_n. note 1 - 2: the control signal , when reading data , is a combination of cs_n and rd_n. note 1 - 3: rd_n, wr0_n, and wr1_n should not be timed to fall when cs_n is rising. similarly, cs_n should not be timed to fall when rd_n or wr0_n, and wr1_n are rising. in the a bove instances, an interval of at least 10ns must be left open.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 128 of 142 jun 28,2013 4.11.2 cpu access timing ( w hen a multiplex bus is set) 4.11.2.1 cpu access write timing ( w hen a multiplex bus is set) tw (cycle1) 47 -1 ad6-ad1 / d15-d0 cs_n wr1_n, wr0_n note 2- 1 ale tsu (a - ale) 32 th (a - ale) 35 tsu (d) 43 th (d) 44 tw (ale) 36 tdwr (ale - ctrl) 37 tw (ctrl) 39 trec (ale) 38 note 2- 3 address determination data determination address determination 4.11.2.2 cpu access read timing ( w hen a multiplex bus is set) tw (cycle1) 47 -1 32 cs_n rd_n note 2- 2 ale tsu (a - ale) th (a - ale) 35 tw (ale) 36 tdwr (ale - ctrl) 37 ten (ctrl - d) 5 ta (ctrl - d) 3 tv (ctrl - d) 4 tdis (ctrl - d) 6 twr (ctrl) 42 trec (ale) 38 note 2- 3 data determination a d d r e s s d e t e r m i n a t i o n a d d r e s s d e t e r m i n a t i o n ad6-ad1 / d15-d0 note 2 - 1: the control signal when writing data is a combination of cs_n, wr1_n, and wr0_n. note 2 - 2: the control signal when reading data is a combination of cs_n and rd_n. note 2 - 3: rd_n, wr0_n, and wr1_n should not be timed to fal l when cs_n is rising. similarly, cs_n should not be timed to fall when rd_n or wr0_n, and wr1_n are rising. in the above instances, an interval of at least 10ns must be left open.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 129 of 142 jun 28,2013 4.11.3 dma access timing (when a cycle steal transfer, s eparate bus are set) 4.11.3.1 dma cycle steal transfer write timing (cpu bus a ddress is not used: dform=010) 17 tdis (ctrl - dreq) twh (dreq) 20 tw (ctrl) 39 tsu (d) th (d) 43 44 dreqi_n (i=0,1) dacki_n (i=0,1) d15-d0 note 3-2 note 3-1 ten (ctrl - dreq) 19 tsu (dend) th (dend) 45 46 dendi_n (i=0,1) note 3-8 data determination dendi_n determintaion wr1 _n, wr0_n 25 40 trec (ctrl ) note 3-10 tdis (pctrlh - dreq) 4.11.3.2 dmacycle steal transfer read timing (cpu bus a ddress not used: dform=010) tdis (ctrl - dreq) twh (dreq) 20 twr (ctrl) ten (ctrl - dreq) 42 tv (ctrl - d) tdis (ctrl - d) ten (ctrl - d) 4 6 19 ta (ctrl - d) dreqi_n (i=0,1) dacki_n (i=0,1) d15-d0 note 3-3 17 5 dendi_n determination ta (ctrl - dendv) 11 tv (ctrl - dendv) 12 3 note 3-8 data determination note 3-1 rd_n dendi_n (i=0,1) note 3 -9 40 trec (ctrl )
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 130 of 142 jun 28,2013 4.11.3.3 dma cycle steal transfer write timing (cpu sepa rate bus setting:dform=000) 50 tsud (a) thd (a) 51 tw (ctrl) 39 tsu (d) th (d) 43 44 a6-a1 cs_n wr0_n, wr1_n d15-d0 tdis (ctrl - dreq) twh (dreq) 20 ten (ctrl - dreq) 19 dreqi_n (i=0,1) note 3-5 tsu (dend) th (dend) 45 46 dendi _n (i=0,1) note 3-7 data determination dendi_n determination address determination note 3-1 17 25 40 trec (ctrl ) note 3-10 tdis (pctrlh - dreq) 4.11.3.4 dma cycle steal transfer read timing (cpu s eparate bus setting: dform=000) 31 tsur (a) thr (a) 34 twr (ctrl) 42 tv (ctrl - d) tdis (ctrl - d) 5 ten (ctrl - d) 4 6 ta (ctrl - d) 3 ta (a) 1 note 3-6 2 tv (a) tdis (ctrl - dreq) 17 twh (dreq) 20 ten (ctrl - dreq) 19 note 3-7 ta (ctrl - dendv) 11 tv (ctrl - dendv) 12 data determination cs_n rd_n d15-d0 dreqi_n (i=0,1) dendi _n (i=0,1) a6-a1 address determination note 3-1 dendi_n detemination note 3 -9 40 trec (ctrl )
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 131 of 142 jun 28,2013 4.11.3.5 dma cycle steal transfer write timing (split bus: dform=100, obus=1/0) 17 tdis (ctrl - dreq) twh (dreq) 20 tw (ctrl) 39 tsu (d) th (d) 43 44 dreqi_n (i=0, 1) sd7-sd0 data determination note 3-1 ten (ctrl - dreq) 19 tsu (dend) th (dend) 45 46 dendi_n (i=0, 1) dendi determination dacki_n (i=0,1) 40 trec (ctrl ) 4.11.3.6 dma cycle steal transfer read timing (split bus: dform=100, obus=1) tdis (ctrl - dreq) twh (dreq) 20 twr (ctrl) ten (ctrl - dreq) 42 tv (ctrl - d) tdis (ctrl - d) ten (ctrl - d) 4 6 19 ta (ctrl - d) dreqi_n (i=0, 1) sd7-sd0 note 3-1 17 5 dendi_n determination tv (ctrl - dend) 14 ten (ctrl - dend) ta (ctrl - dend) 15 tdis (ctrl - dend) 16 3 13 dendi_n (i=0, 1) dacki_n (i=0,1) data determination 40 trec (ctrl )
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 132 of 142 jun 28,2013 4.11.3.7 dma cycle steal transfer read timing (split bus: dform=100, obus=0) tdis (ctrl - dreq) twh (dreq) 20 twr (ctrl) ten (ctrl - dreq) 42 tv (ctrl - dv) 10 19 ta (ctrl - dv) 17 9 ta (ctrl - dendv) 11 tv (ctrl - dendv) 12 note 3-1 data determination dendi_n determination dreqi_n (i=0, 1) sd7-sd0 dendi_n (i=0, 1) dacki_n (i=0, 1) td (dreq - dv) td (dreq - dendv) 23 24 dma transfer begins note 3-9 note 3-9 40 trec (ctrl ) 4.11.3.8 dma cycle steal transfer w rite timing (cpu bus a ddress not used: dform=011) 17 tdis (ctrl - dreq) twh (dreq) 20 tw (ctrl) 39 tsu (d) th (d) 43 44 dreqi_n (i=0,1) d15-d0 note 3-8 note 3-1 ten (ctrl - dreq) 19 tsu (dend) th (dend) 45 46 dendi_n (i=0,1) data determination dendi determination dacki_n (i=0,1) 40 trec (ctrl)
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 133 of 142 jun 28,2013 4.11.3.9 dma cycle steal transfer read timing (cpu bus a ddress not used: dform=011) tdis (ctrl - dreq) twh (dreq) 20 twr (ctrl) ten (ctrl - dreq) 42 tv (ctrl - d) tdis (ctrl - d) ten (ctrl - d) 4 6 19 ta (ctrl - d) dreqi_n (i=0,1) d15-d0 note 3-8 17 5 dendi_n determination ta (ctrl - dendv) 11 tv (ctrl - dendv) 12 3 data determination note 3-1 dacki_n (i=0,1) dendi_n (i=0,1) note 3-9 40 trec (ctrl) note 3 -1: the control signal is the inactive condition for dreqi_n (i=0, 1). when the next dma tran sfer exists , the delay ratings for twh (dreq) and ten (ctrl - dreq) will be valid until dreqi_n becomes active is twh (dreq). note 3 -2: the control signal when writing data is a combination of dacki_n, wr1_n, and wr0_n. note 3 -3: the control signal when read ing data is a combination of dacki_n and rd_n. note 3 -4: the control signal when writing data is a combination of dack0 and dstrb0_n. note 3 -5: the control signal when writing data is a combination of cs_n, wr0_n and wr1_n. note 3 -6: the control signal whe n reading data is a combination of cs_n and rd_n. note 3 -7: rd_n, wr0_n and wr1_n should not be timed to fall when cs_n is rising. similarly, cs_n should not be timed to fall when rd_n or wr0_n and wr1_n are rising. in the instances noted above, an interva l of at least 10ns must be left open. note 3 -8: rd_n, wr0_n and wr1_n should not be timed to fall when dacki_n is rising (or falling). similarly, dack should not be timed to fall (or rise) when rd_n or wr0_n and wr1_n are rising. in the instances noted abo ve, an interval of at least 10ns must be left open. note 3 -9: when the receipt data is one byte, the data determined time is "(23)td(dreq - dv)" and the dend determined time is "(24)td(dreq - dendv)". note 3 - 10: the time required ultil dreqi_n (i=0,1) becomes active is valid, when the next dma transfer exists , and when tdis (ctrl - dreq) or tdis (pctrlh - dreq) has slow ratings.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 134 of 142 jun 28,2013 4.11.4 dma access timing (cycle steal transfer, w hen a multiplex bus is set) 4.11.4.1 dma c ycle steal transfer write timing (cpu m ultiplex bus settings : dform=000) tdis ( ctrl - dreq ) twh ( dreq ) 17 20 ten ( ctrl - dreq ) 19 dreqi _ n (i = 0 , 1 ) tsu ( dend ) th ( dend ) 45 46 dendi _ n (i = 0 , 1 ) dendi _ n determination ad 6 -ad 1 / d 15- d 0 cs _ n note 4 -1 address determination ale tsu ( a - ale ) 32 th ( a - ale ) 35 tsu (d ) 43 th (d ) 44 tw ( ale ) 36 37 tw ( ctrl ) 39 trec ( ale) 38 note 4 -3 tdwr ( ale - ctrl ) address determination data determination wr 1 _ n , wr 0 _ n 25 tdis ( pctrlh - dreq ) note 4 -5 4.11.4.2 dma cycle steal transfer read timing (cpu multiplex bus setting:dform=000) dreqi_n (i=0,1) tdis (ctrl - dreq) 17 twh (dreq) 20 ten (ctrl - dreq) 19 32 a6-a1 / d15-a0 cs_n rd_n note 4-2 a d d r e s s d e t e r m i n a t i o n ale tsu (a - ale) th (a - ale) 35 tw (ale) 36 tdwr (ale - ctrl) 37 ten (ctrl - d) 5 ta (ctrl - d) 3 tv (ctrl - d) 4 tdis (ctrl - d) 6 twr (ctrl) 42 trec (ale) 38 note 4-3 dendi _n (i=0,1) ta (ctrl - dendv) 11 tv (ctrl - dendv) 12 data determination address determination dendi_n determination note 4-4 note 4 -1: the control signal when writing data is a combination of cs_n, wr0_n, and wr1_n. note 4 -2: the cont rol signal when reading data is a combination of cs_n and rd_n. note 4 - 3: rd_n, wr0_n and wr1_n should not be timed to fall when cs_n is rising. similarly, cs_n should not be timed to fall when rd_n or wr0_n and wr1_n are rising. in the instances noted abo ve, an interval of at least 10ns must be left open. note 4 - 4 : when the receipt data is one byte, the dend determined time is "(24)td(dreq - dendv)". note 4 - 5: the time required until dreqi_n (i=0,1) becomes active is valid, when the next dma transfer exists , and when tdis (ctrl - dreq) or tdis (pctrlh - dreq) has slow ratings.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 135 of 142 jun 28,2013 4.11.5 dma access timing ( b urst transfer and s eparate bus are set) 4.11.5.1 dma b urst transfer write timing (cpu bus a ddress not used: dform=010) 18 tdis (ctrlh - dreq) tw (ctrl_b) 48 tsu (d) th (d) 43 44 dreqi_n (i=0,1) dacki_n (i=0,1) d15-d0 note 5-1 d0 tsu (dend) th (dend) 45 46 dendi_n (i=0,1) trec (ctrl_b) tw (cycle1) 49 47 - 1 d1 dn d2 wr1_n, wr0_n 17 tdis (ctrl - dreq) note 5-8 25 tdis (pctrlh - dreq) note 5-9 4.11.5.2 dma b urst transfer read ti ming (cpu bus a ddress not used: dform=010) 17 tdis (ctrl - dreq) tw (ctrl_b) 48 ta (ctrl - d) tv (ctrl - d) 4 3 dreqi_n (i=0,1) dacki_n (i=0,1) rd_n d15-d0 note 5-2 d0 ta (ctrl - dendv) tv (ctrl - dendv) 12 dendi _n (i=0,1) trec (ctrl_b) tw (cycle1) 49 47 -1 d1 11 dn-1 dn note 5-8 note 5-6
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 136 of 142 jun 28,2013 4.11.5.3 dma burst transfer write timing (separate bus setting:dform=000) tdis (pctrlh - dreq) note 5-9 18 tdis (ctrlh - dreq) tw (ctrl_b) 48 tsu (d) th (d) 43 44 dreqi _n (i=0,1) cs_n wr0_n, wr1_n d15-d0 note 5-4 d0 tsu (dend) th (dend) 45 46 dendi _n (i=0,1) trec (ctrl_b) tw (cycle1) 49 47 -1 d1 dn tsud (a) thd (a) 50 51 a6-1 address determination address determination address determination address determination d2 17 tdis (ctrl - dreq) note 5-7 25 4.11.5.4 dma b urst transfer read timing ( s eparate bus setting: dform=000) tw (ctrl_b) 48 ta (ctrl-d) tv (ctrl-d) 4 3 a6-a1 cs_n rd_n d15-d0 note 5 -5 d0 ta (ctrl - dendv) tv (ctrl - dendv) 11 12 dendi_n (i=0,1) trec (ctrl_b) tw (cycle1) 49 47 -1 d1 17 tdis (ctrl - dreq) dreqi_n (i=0,1) address determination address determination tsur (a) thr (a) 31 34 ta (a) tv (a) 2 1 dn-1 dn address determination address determination note 5 -7 note 5 -6
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 137 of 142 jun 28,2013 4.11.5.5 dma b urst transfer write timing (split bus: dform=100, obus=1/0) 18 tdis (ctrlh - dreq) tw (ctrl_b) 48 tsu (d) th (d) 43 44 dreqi_n (i=0, 1) dacki_n (i=0, 1) sd7-sd0 d0 tsu (dend) th (dend) 45 46 dendi_n (i=0, 1) trec (ctrl_b) tw (cycle2) 49 47 -2 d1 dn d2 17 tdis (ctrl - dreq) 4.11.5.6 dmaburst transfer read timing (split bus:dform=100, obus=1) 17 tdis (ctrl - dreq) tw (ctrl_b) 48 ta (ctrl - d) tv (ctrl - d) 4 3 dreqi_n (i=0, 1) dacki_n (i=0, 1) sd7-sd0 d0 ta (ctrl - dend) tv (ctrl - dendv) 13 14 dendi_n (i=0, 1) trec (ctrl_b) tw (cycle2) 49 47 -2 d1 dn-1 dn
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 138 of 142 jun 28,2013 4.11.5.7 dma b urst transfer r ead timing (split bus: dform=100, obus=0) 17 tdis (ctrl - dreq) tw (ctrl_b) 48 ta (ctrl - dv) tv (ctrl - dv) 10 9 dreqi_n (i=0, 1) dacki_n (i=0, 1) sd7-sd0 d0 ta (ctrl - dendv) tv (ctrl - dendv) 11 dendi_n (i=0, 1) trec (ctrl_b) tw (cycle2) 49 47 -2 d1 12 dn dn-1 td (dreq - dv) 23 td (dreq - dendv) 24 note 5 -6 note 5 -6
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 139 of 142 jun 28,2013 4.11.5.8 dma b urst transfer write timing (cpu bus a ddress not used: dform=011) 18 tdis (ctrlh - dreq) tw (ctrl_b) 48 tsu (d) th (d) 43 44 dreqi_n (i=0,1) d15-d0 d0 tsu (dend) th (dend) 45 46 dendi_n (i=0,1) trec (ctrl_b) tw (cycle2) 49 47 -2 d1 dn d2 dacki_n (i=0,1) 17 tdis (ctrl - dreq) 4.11.5.9 dma b urst transfer read timing (cpu bus a ddress not used: dform=011) 17 tdis (ctrl - dreq) tw (ctrl_b) 48 ta (ctrl - d) tv (ctrl - d) 4 3 dreqi_n (i=0,1) dacki_n (i=0,1) d15-d0 d0 ta (ctrl - dendv) tv (ctrl - dendv) 12 dendi _n (i=0,1) trec (ctrl_b) tw (cycle2) 49 47 -2 d1 11 dn-1 dn note 5 -6 note 5 - 1 : the control signal when writing data is a combination of dacki_n(i=0, 1), wr0_n and wr1_n. note 5 - 2 : the control signal when reading data is a combination of dacki_n and rd_n. note 5 - 3 : the control signal when writing data is a combination of dack0 and dstrb0_n. note 5 -4 : the control signal when writing data is a combination of cs_n, wr0_n and wr1_n. note 5 - 5 : the control signal when reading data is a combination of cs_n and rd_n. note 5 - 6 : when the receipt data is one byte, the data determined time is "(23)td(dreq - dv)" and the dend determined time is "(24)td(dreq - dendv)". note 5 - 7: rd_n, wr0_n and wr1_n should not be timed to fall when cs_n is rising. similarly, cs_n should not be timed to fall when rd_n, wr0_n and wr1_n are rising. in the instances noted above, an inter val of at least 10ns must be left open. note 5 - 8: rd_n, wr0_n and wr1_n should not be timed to fall when dacki_n is rising (or falling) . similarly, dacki_n should not be timed to fall (or rise) when rd_n, wr0_n and wr1_n are rising. in the instances noted above, an interval of at least 10ns must be left open. note 5 - 9:the time required until dreqi_n (i=0,1) becomes active is valid, when the next dma transfer exists , and when tdis (ctrl - dreq) or tdis (pctrlh - dreq) has slow ratings.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 140 of 142 jun 28,2013 4.11.6 dma access timing ( b urs t transfer, w hen a multiplex bus is set) 4.11.6.1 dma b urst transfer w rite timing (cpu m ultiplex bus setting: dform=000) tdis (ctrlh - dreq) tw (ctrl_b) 48 tsu (d) th (d) 43 44 dreqi_n (i=0, 1) cs_n wr0_n, wr1_n note 6-1 tsu (dend) th (dend) 45 46 dendi_n (i=0, 1) trec (ctrl_b) tw (cycle1) 49 47 -1 tsu (a - ale) thw (a - ale) 32 35 ad6-ad1 / d15-d0 address address d0 ale tw (ale) 36 tdwr (ale_ctrl) 37 note 6-3 dn d1 address 17 tdis (ctrl - dreq) 25 18 tdis (pctrlh - dreq) note 6- 5 4.11.6.2 dma b urst transfer read timing (cpu m ultiplex bus setting: dform=000) 17 tdis (ctrl - dreq) tw (ctrl_b) 48 ta (ctrl-d) tv (ctrl-d) 3 4 dreqi_n (i=0, 1) cs_n rd_n note 6-2 ta (ctrl - dendv) tv (ctrl - dendv) 11 12 dendi_n (i=0, 1) trec (ctrl_b) tw (cycle1) 49 47 -1 tsu (a - ale) th (a - ale) 32 35 ad6-ad1 / d15-d0 address d0 ale tw (ale) 36 tdwr (ale_ctrl) 37 note 6-3 dn d1 address address note 6-4 note 6 -1: the co ntrol signal when writing data is a combination of cs_n, wr0_n and wr1_n. note 6 -2: the control signal when reading data is a combination of cs_n and rd_n. note 6 -3: rd_n, wr0_n and wr1_n should not be timed to fall when cs_n is rising. similarly, cs_n sho uld not be timed to fall when rd_n or wr0_n and wr1_n are rising. in the instances noted above, an interval of at least 10ns must be left open. note 6 -4 : when the receipt data is one byte, the dend determined time is "(24)td(dreq - dendv)". note 6 - 5:the tim e required until dreqi_n (i=0,1) becomes active is valid, when the next dma transfer exists , and when tdis
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 141 of 142 jun 28,2013 (ctrl - dreq) or tdis (pctrlh - dreq) has slow ratings.
r8a66593 fp/bg r19ds0071ej0101 rev1.01 p age 142 of 142 jun 28,2013 4.12 interrupt t iming td (ctrl - int) note 7-1 twh (int) int_n cs_n, wr0_n, wr1_n 22 21 note7 -1: writing using the combination of cs_n, wr0_n and wr1_n takes plac e during the active ("l") overlap period. the ratings from the rising edge are valid starting from the earliest change in the inactive signal.
all trademarks and registe red trademarks are the property of their respective owners. c - 1 revision history r8a66593 data sheet rev. date description page summary 1.00 o ct 26, 2012 rev. 1.00 issu ed 1.01 j un 28 ,2013 p.14 add dcfm bit to bit symbol list. p.16 add dcfm bit to syscfg0 register. p.43 add process at the time of attach/detach in section 2.11. 1.
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